Hybrid Counter Code Generator for High-Speed Synchronized Output
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Solution Overview
Problem
Existing code generators face challenges in operating at high speeds and low power conditions due to the limitations of synchronous counters, which are restricted by combinational logic circuits and propagation delays, especially when the number of code bits increases or supply voltage levels decrease.
Innovation Solution
A code generator that combines an asynchronous counter and a synchronous counter, where the asynchronous counter divides the clock signal to generate a lower frequency for the synchronous counter, allowing simultaneous output of code bits and reducing the frequency restrictions caused by combinational logic circuits, thereby enabling operation at high speeds and low power conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a synchronous counter is used to output synchronized code bits, then the code output is synchronized with the clock signal, but the counter cannot operate at high speeds due to propagation delays in combinational logic circuits
Solution Approach 1:
The counter is divided into two segments: an asynchronous counter that divides the clock signal to generate a lower-frequency clock, and a synchronous counter that operates at this reduced frequency. This segmentation allows the synchronous counter to operate reliably within its speed limitations while still providing synchronized code output, thereby resolving the contradiction between synchronization reliability and operating speed.
Solution Approach 2:
An asynchronous counter acts as an intermediary between the high-frequency input clock and the synchronous counter. It divides the high-frequency clock signal to generate a lower-frequency clock that the synchronous counter can handle, mediating the speed mismatch and enabling the synchronous counter to operate at achievable speeds while maintaining code synchronization.
2Speed
If an asynchronous counter is used to operate at high speeds, then the counting operation is fast, but the output code is not synchronized with the clock signal
Solution Approach 1:
The counter system is segmented into an asynchronous portion (first counter dividing the clock) and a synchronous portion (second counter generating synchronized code). This segmentation allows the asynchronous part to handle high-speed clock division while the synchronous part ensures reliable synchronized code output, resolving the contradiction between speed and synchronization.
3Quantity of substance
If the number of code bits is increased to enhance functionality, then the code generator provides more information, but the propagation delay in synchronous counters increases
Solution Approach 1:
By segmenting the counter into asynchronous and synchronous portions, the system can handle a larger number of code bits without proportionally increasing the operating speed requirements. The asynchronous counter divides the clock frequency, allowing the synchronous counter to manage more bits at a reduced, achievable speed.
Solution Approach 2:
The system changes the clock frequency parameter by using the asynchronous counter to divide the input clock before it reaches the synchronous counter. This parameter change allows the synchronous counter to handle more code bits by operating at a lower, manageable frequency rather than attempting to process all bits at the original high frequency.
Data Source
AI summary
A code generator includes an asynchronous counter that includes first to m-th flip-flops configured to asynchronously output first to m-th output signals in response to a first clock signal, the first to m-th output signals corresponding to first to m-th bits (m being an integer of 2 or more) of a code, respectively, and a synchronous counter that includes (m+1)-th to (m+n)-th flip-flops configured to synchronously output (m+1)-th to (m+n)-th output signals in response to the first clock signal, the (m+1)-th to (m+n)-th output signals corresponding to (m+1)-th to (m+n)-th bits (n being an integer of 2 or more) of the code. The asynchronous counter further includes first to m-th delay circuits configured to respectively delay the first to m-th output signals such that the first to m-th bits of the code are output together at the same time when the (m+1)-th to (m+n)-th bits are output.