Hybrid CRC Circuit for Faster Checksums With Lower Area
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Solution Overview
Problem
Existing CRC circuits face limitations in flexibility and re-usability, particularly in serial transmission protocols like SPI, due to dependencies on seed values and clock cycles, leading to inefficiencies in computing CRC checksums.
Innovation Solution
A hybrid serial/combinational architecture that combines a linear-feedback shift register (LFSR) for serial CRC processing with a cascaded arrangement of combinational circuits for parallel processing, allowing CRC computation in N clock cycles without seed restrictions, using the same CRC polynomial for both stages and null input data in the parallel stage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a serial CRC circuit (LFSR) is used, then the circuit occupies less semiconductor area, but it requires more clock cycles to compute CRC
Solution Approach 1:
The CRC computation is divided into two segments: a serial processing stage using LFSR that handles the initial CRC calculation, and a parallel processing stage using combinational logic that completes the computation. This segmentation allows the circuit to achieve faster overall computation than pure serial while maintaining area efficiency better than pure parallel designs.
Solution Approach 2:
The patent merges serial and parallel processing approaches into a hybrid architecture. The serial LFSR stage and parallel combinational stage are combined to work together, leveraging the area efficiency of serial processing and the speed of parallel processing to resolve the contradiction between area and time.
2Loss of time
If a parallel CRC circuit (combinational) is used, then the computation is faster, but it occupies more semiconductor area
Solution Approach 1:
The parallel processing capability is segmented and applied only to the second stage of CRC computation. Instead of using full parallel processing for the entire computation, the patent segments the work so that only the finalization stage uses parallel combinational logic, reducing area requirements while maintaining speed advantages.
Solution Approach 2:
The patent applies partial parallel processing rather than complete parallel processing. By using parallel combinational logic only for the second stage (partial action) rather than the entire CRC computation, the circuit achieves speed improvement without the full area penalty of a completely parallel design.
3Adaptability or versatility
If seed restrictions are imposed, then the CRC circuit can be simplified, but it reduces flexibility and re-usability
Solution Approach 1:
The hybrid architecture provides universal functionality by handling both restricted and unrestricted seed cases. The circuit can operate with any seed value (full versatility) while using optimization techniques where applicable, achieving multi-functionality that resolves the contradiction between flexibility and complexity.
Solution Approach 2:
The patent changes the parameter of seed restriction from a fixed constraint to a variable condition. The circuit adapts its operation based on whether seed restrictions apply, allowing it to optimize for simplicity when restrictions are present while maintaining full flexibility when they are not, thus resolving the contradiction.
Data Source
AI summary
A device includes serial cyclic redundancy check (CRC) processing circuitry and parallel CRC processing circuitry. The serial CRS processing circuitry, in operation, generates a set of intermediate CRC bits based on a first set of seed bits and input data. The parallel CRC processing circuitry is coupled to the serial CRC processing circuitry, and, in operation, generates, using the set of intermediate CRC bits as a set of parallel seed bits and using null input bits, a set of output CRC bits corresponding to the input data.