Hybrid CXL Type-3 SSD Memory Device Command Latency
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Solution Overview
Problem
Conventional memory systems experience undesirable command latencies due to the need for memory devices to access system memory for command retrieval, which slows down the execution of NVMe commands.
Innovation Solution
Implementing a hybrid CXL Type-3 SSD memory device with a local device attached memory (DAM) that hosts submission queues (SQs) and completion queues (CQs), allowing these queues to be memory-mapped to the host, thereby reducing the need for system memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If NVMe commands are stored in system memory and retrieved by the memory device, then the system can maintain a conventional memory architecture, but command latencies increase due to the need to hop to system memory for command retrieval
Solution Approach 1:
The patent embeds device-attached memory (DAM) within the memory device itself, creating a nested structure where DAM is integrated into the SSD controller. This allows submission queues and completion queues to reside locally within the device rather than in system memory, eliminating the need to hop to system memory for command retrieval and thereby reducing command latencies while maintaining a manageable architecture through this nested integration approach
Solution Approach 2:
The patent introduces a new dimension to the memory hierarchy by adding device-attached memory as an intermediate layer between system memory and the storage medium. This creates a three-level hierarchy (system memory - DAM - storage medium) that adds spatial proximity for command access, reducing latency by placing command queues in a new dimensional space closer to the processing logic within the device
2Productivity
If submission queues and completion queues are allocated in system memory, then the host can manage memory resources centrally, but the memory device must access system memory frequently causing increased command latencies
Solution Approach 1:
The patent extracts the submission queues and completion queues from system memory and relocates them to device-attached memory within the SSD. This extraction removes the dependency on system memory access for command retrieval, allowing the memory device to execute commands at higher speeds without the time penalty of frequent system memory hops, thereby improving productivity while reducing memory access time
3Reliability
If the memory device accesses system memory for command retrieval, then the system maintains a unified memory management approach, but command latencies are undesirably increased
Solution Approach 1:
The patent introduces device-attached memory as an intermediary layer between system memory and the storage processing logic. This intermediary holds submission queues and completion queues locally, mediating between the host's command submission needs and the storage operations. It maintains reliable command execution by providing a dedicated local buffer while eliminating the time-consuming direct access to system memory for each command retrieval
Data Source
AI summary
Provided is a memory device, a method and a system that includes a host in communication with a system memory having a driver that creates commands for writing and reading data, and the memory device in communication with the host that includes a memory array including a plurality of memory components, a device attached memory including a submission queue and a completion queue for receiving commands from the driver, and a device controller configure to communicate with the device attached memory, the host and the plurality of memory components, such that the device controller receives an interface or link from the driver indicative of commands being placed into the submission queue, and automatically executes any pending commands therein for completion.