Hybrid Data-Centric Architecture Offloading Computation to DPUs
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Solution Overview
Problem
The CPU-based model of calculation introduces limitations such as cache coherence issues, memory wall, and data moving problems, hindering improved computation performance in data processing.
Innovation Solution
A hybrid data-centric architecture is introduced, featuring a CPU, short-term memory, mid-term memory, and data processing units (DPUs) that offload computation to DPUs near persistent memory, enabling efficient data pattern recognition and knowledge synthesis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU-based calculation model is used, then data processing can be performed, but computation performance is hindered due to cache coherence issues, memory wall, and data moving problems
Solution Approach 1:
The patent segments the monolithic CPU-based computation model into separate functional units: CPU for control, DPUs for data processing, and a hierarchical memory system (short-term memory, mid-term memory, long-term memory). This segmentation allows each component to specialize in its optimal function, resolving the contradiction between productivity and device complexity by distributing workload appropriately across segmented components.
Solution Approach 2:
The patent introduces DPUs as intermediary components between the CPU and persistent memory. These DPUs handle data processing tasks locally near the memory, acting as mediators that eliminate the need for data to travel to the CPU, thereby solving the memory wall problem and improving computation performance without increasing overall system complexity.
2Productivity
If data is moved between memory and CPU, then processing can occur, but data moving problems and memory wall issues arise
Solution Approach 1:
The patent implements preliminary action by pre-fetching and pre-processing data in the hierarchical memory system before the CPU needs it. The short-term memory and mid-term memory layers prepare data in advance, so when the CPU requires data, it is already available, eliminating data transfer delays and improving processing speed without sacrificing time.
Solution Approach 2:
DPUs serve as intermediaries that perform data processing operations locally within the memory hierarchy, eliminating the need for continuous data movement between memory and CPU. This intermediary approach allows data to be processed where it resides, dramatically reducing data transfer time while maintaining high processing speeds.
3Productivity
If CPU handles all computation, then data processing can be performed, but CPU load becomes excessive and performance is limited
Solution Approach 1:
The patent segments the computation workload by separating CPU functions (control and coordination) from DPU functions (data processing). This segmentation distributes the computational burden across multiple specialized units, reducing CPU load and energy consumption while maintaining or improving overall computation throughput through parallel processing capabilities.
Solution Approach 2:
The patent implements multi-functionality by designing DPUs that can handle various data processing tasks locally, reducing the need for CPU intervention. This universal approach allows the same DPU architecture to perform multiple processing functions, improving throughput while keeping CPU energy consumption low since the CPU only handles high-level coordination.
Data Source
AI summary
The present disclosure describes techniques for offloading data processing and knowledge synthesis. A set of flags may indicate information about the memory pages in a first memory and may be manageable by at least one central processing unit (CPU). A memory page may be flushed to a second memory if the memory page is associated with a first flag. The first flag may indicate that the memory page is ready to be flushed to the second memory. The second memory may be configured to store a sequence of states of each of the memory pages. Data patterns and relations among the data patterns may be determined by data processing units (DPUs) based on the sequence of states of each of the memory pages. A knowledge base may be built in a third memory based on the data patterns and the relations among the data patterns.