Hybrid Data Latch Switching Between Pulse and Master-Slave Modes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing data storage circuits in processors face challenges in operating efficiently across a wide range of power supply voltage levels and frequencies, particularly in battery-powered devices, as they either consume excess power or perform poorly in reduced power modes, limiting their use in high-frequency and low-voltage applications.
Innovation Solution
A hybrid data storage circuit that operates as a pulse latch for high-frequency modes and switches to a master-slave flip-flop for reduced power modes, sharing circuitry to reduce additional circuitry and power consumption, while allowing operation over a broad range of conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a data storage circuit is designed to capture data with narrow setup and hold times for high frequency operation, then the circuit can operate at high frequencies, but it performs poorly over a broad range of power supply voltage levels
Solution Approach 1:
The circuit dynamically switches between two operational modes (pulse latch mode and master-slave flip-flop mode) based on operating conditions. The control signal selectively enables different circuit paths to optimize performance for either high-frequency operation or broad voltage range operation, making the circuit adaptable to varying power supply conditions while maintaining high-speed capability when needed
2Use of energy by moving object
If a data storage circuit is designed for reduced power consumption, then power efficiency improves, but the circuit cannot operate effectively at high frequencies
Solution Approach 1:
The circuit employs dynamic mode switching where the control signal activates either a low-power master-slave flip-flop configuration or a high-speed pulse latch configuration based on the required operating frequency and power constraints, enabling the circuit to optimize the trade-off between power consumption and operating speed
Solution Approach 2:
The circuit changes its operational parameters by switching between different clocking schemes (continuous clocking for high-frequency mode versus pulsed clocking for low-power mode), allowing it to adapt its power consumption and speed characteristics to match the operational requirements
3Reliability
If separate circuits are used for pulse latch and master-slave flip-flop functions, then each circuit can be optimized for its specific function, but the total circuit area and complexity increases
Solution Approach 1:
The circuit merges the pulse latch and master-slave flip-flop functionalities into a single unified structure that shares common circuit elements. The control signal selectively activates different operational paths within the same circuit, eliminating the need for separate dedicated circuits while maintaining the functional benefits of both configurations
Solution Approach 2:
The unified circuit is designed to perform multiple functions (pulse latch operation and master-slave flip-flop operation) through a single structure that can be configured via the control signal, reducing overall circuit area while maintaining the optimization benefits of both operational modes
Data Source
AI summary
An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.