Hybrid Data Transmission Circuit With Single-VCO Multiphase PLL
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Solution Overview
Problem
Hybrid LVDS circuits face challenges in supporting multiple interface standards with different parallel-to-serial conversion ratios, leading to high circuit area and cost due to the need for multiple VCO circuits, making it difficult to increase speed and reduce power consumption.
Innovation Solution
A hybrid data transmission circuit design that utilizes a single multiphase VCO circuit to generate and output different multiphase clocks, allowing a single PLL circuit unit to support various conversion ratios, thereby reducing circuit area and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple VCO circuits are provided to support different parallel-to-serial conversion ratios, then multiple interface standards can be supported, but the circuit area and cost increase
Solution Approach 1:
The patent applies universality by designing a single VCO circuit that can generate multiple clock frequencies (135 MHz for std-LVDS and 240 MHz for mini-LVDS) and a single PLL circuit that can be configured for different parallel-to-serial conversion ratios (7:1 and 4:1). This multi-functional design eliminates the need for separate VCO circuits for each interface standard, thereby reducing circuit area while maintaining support for multiple standards
Solution Approach 2:
The patent employs dynamics by making the PLL circuit configurable through control signals that dynamically adjust the parallel-to-serial conversion ratio based on the selected interface standard. The system can switch between different conversion ratios (7:1 for std-LVDS, 4:1 for mini-LVDS) and clock frequencies without requiring hardware changes, enabling adaptive support for multiple standards using a fixed circuit structure
2Speed
If a single-clock architecture with high-speed VCO is used, then parallel-to-serial conversion can be performed at high speed, but power consumption increases
Solution Approach 1:
The patent uses dynamics by implementing a multiphase clock architecture where the VCO operates at a lower base frequency and multiple phase-shifted clocks are generated to achieve high-speed parallel-to-serial conversion. This dynamic approach allows the system to maintain high conversion speeds while reducing the power consumption compared to a single high-frequency clock architecture
Solution Approach 2:
The patent applies segmentation by dividing the single high-speed clock into multiple phase-shifted clocks. Instead of using one high-frequency clock that consumes more power, the system segments the clocking function across multiple lower-frequency phases, achieving the same high-speed conversion performance with reduced power consumption
3Productivity
If parallel-to-serial conversion circuit operates at high speed, then conversion performance is improved, but increasing speed becomes difficult
Solution Approach 1:
The patent applies segmentation by breaking down the high-speed conversion task into multiple parallel operations using phase-shifted clocks. Each clock phase handles a portion of the parallel data bits, allowing the conversion circuit to operate at lower individual speeds while achieving high overall conversion performance through coordinated parallel processing
Data Source
AI summary
A data transmitter having a parallel-to-serial conversion function is supplied with a clock by a PLL circuit unit. In the PLL circuit unit, a first multiphase clock supplied to a first parallel-to-serial conversion circuit is generated and output by a multiphase VCO circuit, while a second multiphase clock supplied to a second parallel-to-serial conversion circuit is generated and output by a multiphase clock generator. The multiphase clock generator generates the second multiphase clock based on the clock output from the multiphase VCO circuit.