Hybrid Dataflow Timed Domain System for FPGA Bottlenecks
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Solution Overview
Problem
The performance of FPGAs is limited by disparities between the operating parameters of embedded processors and FPGA fabric, leading to bottlenecks and reduced flexibility due to the integration of ASIC cores, which compromise on performance and design flexibility.
Innovation Solution
A hybrid dataflow timed domain system is implemented, where a first dataflow network block processes input data to output untimed tokens, which are written and read from storage with timed parameters, and fed back to control the token generation rate, enabling interfacing between temporal and non-temporal domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If embedded processors are integrated into FPGA fabric, then overall system performance is improved, but performance disparities between processor and fabric create bottlenecks
Solution Approach 1:
The patent introduces a buffer as an intermediary component between the embedded processor and FPGA fabric. This buffer mediates data transfer between the two domains, absorbing performance disparities and preventing bottlenecks. The buffer acts as a shock absorber that decouples the different operating speeds and timing characteristics of the processor and fabric, allowing both to operate at their optimal speeds without directly constraining each other.
2Speed
If ASIC cores are integrated to improve performance, then operating frequency increases, but design flexibility is compromised
Solution Approach 1:
The patent applies local quality by selectively hardening only specific performance-critical paths within the FPGA fabric while keeping other portions programmable. This allows the design to have both high-speed fixed-function blocks (where speed is critical) and flexible programmable logic (where adaptability is needed), creating a hybrid architecture that optimizes both operating frequency and design flexibility in different locations of the device.
3Adaptability or versatility
If dataflow control is implemented with timing parameters, then interfacing between temporal and non-temporal domains is enabled, but system complexity increases
Solution Approach 1:
The patent implements dataflow control by dynamically changing timing parameters (such as clock phases, data width, and transfer timing) based on the specific requirements of interfacing between temporal and non-temporal domains. This allows the system to adapt its operational parameters to match different domain requirements without adding significant structural complexity, using parameter adjustment rather than architectural transformation.
Data Source
AI summary
Dataflow control for an application with timing parameters, including interfacing temporal and non-temporal domains, is described. The domains receive input data to a first dataflow network block, which is processed for untimed output of first tokens. The first tokens are obtained by a memory interface for timed writing of data portions of the first tokens to data storage and for timed reading of the data portions therefrom. Sending of the data portions read to a first queue of a first controller block is untimed, and the data portions are output by the first controller block with physical timing parameters. Second tokens are generated by the first controller block responsive to the physical timing parameters. The second tokens are fed back to a second queue of the first dataflow network block to control rate of generation of the first tokens by the first dataflow network block.