Hybrid Deck SLC NAND Memory Configuration for Storage Optimization

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Solution Overview

Problem

In 3D NAND memory devices, the block-by-deck architecture leads to enhanced hot carrier injection read disturb and inefficient utilization of system-reserved NAND blocks, as all decks are programmed in the same mode, resulting in underutilization and reduced storage capacity.

Innovation Solution

Implementing a hybrid deck SLC NAND memory configuration, where one deck operates in SLC mode for system-specific information while others operate in native modes like TLC or QLC, allowing independent deck operations and reducing the need for spare blocks by configuring bias voltages to mitigate disturbs and optimize storage utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If all decks are programmed in the same mode, then the memory device structure is simple, but the storage capacity is reduced and system-reserved blocks are underutilized

Engineering Contradiction:

Improvememory device structureVSAvoidstorage capacity

Core Design Contradiction:

Device complexityVSQuantity of substance

Solution Approach 1:

The patent applies local quality by allowing different decks within the same memory device to operate in different programming modes. Specifically, one deck operates in SLC mode for system-specific information while other decks operate in native modes (TLC or QLC) for user data, enabling optimized storage capacity and reduced underutilization of system-reserved blocks.

Inventive Principle:

Principle #3Local quality

2Device complexity

If all decks are programmed in the same mode, then the control mechanism is simple, but read disturb is enhanced

Engineering Contradiction:

Improvecontrol mechanismVSAvoidread disturb

Core Design Contradiction:

Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent configures different decks with different programming modes to mitigate read disturb. By having one deck in SLC mode and others in native modes, the control mechanism can selectively operate on specific decks, reducing hot carrier injection read disturb that occurs when all decks are programmed in the same mode.

Inventive Principle:

Principle #3Local quality

3Quantity of substance

If block size is reduced using BBD architecture, then the minimum data unit for erase is reduced, but the number of decks increases and control complexity increases

Engineering Contradiction:

Improveminimum data unit sizeVSAvoidcontrol complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent manages control complexity by implementing selective deck operation. Instead of uniformly controlling all decks, the system can target specific decks for SLC or native mode operations, simplifying the control mechanism while maintaining the benefits of reduced block size through BBD architecture.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20230376215A1Multi-deck NAND memory with hybrid deck slc

Publication Date: 2023.11.23 INTEL NDTM US LLC

AI summary

An example of a memory device may comprise NAND media with a plurality of decks, and circuitry coupled to the NAND media to control access to a superblock of memory cells aligned along a pillar of the NAND media, wherein the superblock includes at least a first block that corresponds to memory cells aligned along the pillar in a first deck of the plurality of decks and a second block that corresponds to memory cells aligned along the pillar in a second deck of the plurality of decks, configure the NAND media in a first program mode for the first block of the superblock, and configure the NAND media in a second program mode for the second block of the superblock. Other examples are disclosed and claimed.