Hybrid Deferred Assertion Logic Simulation EDA
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Solution Overview
Problem
Existing electronic design automation (EDA) applications face challenges in converting simple immediate assertions (SIAs) into hybrid deferred assertions (HDAs), particularly in low power circuit designs with multiple power domains, leading to race conditions and erroneous information due to power state changes during simulation.
Innovation Solution
A logic simulation EDA application that converts SIAs into HDAs, allowing for the recording of state changes during active simulation cycles and deferring the reporting of results to reactive cycles, ensuring accurate and granular reporting by marking assertions as suspended or inactive during power state changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simple immediate assertions (SIAs) are used in low power circuit designs with multiple power domains, then the assertion evaluation is simple and immediate, but race conditions occur and erroneous information is generated due to power state changes during simulation
Solution Approach 1:
The assertion evaluation process is segmented into distinct phases: active region evaluation, power state change detection, and reactive region reporting. This segmentation allows the system to separate the evaluation of assertion conditions from the reporting of results, preventing race conditions by ensuring that power state changes are properly detected and handled between these phases.
Solution Approach 2:
The system performs preliminary detection of power state changes during the active region evaluation phase, before proceeding to report results in the reactive region. This preliminary action ensures that the assertion evaluation is based on the correct power domain state, preventing erroneous information from being generated due to undetected power transitions.
2Productivity
If assertion results are reported immediately during active simulation cycles, then the reporting is prompt, but race conditions occur due to power state changes
Solution Approach 1:
The reporting function is extracted from the immediate active region evaluation and moved to the reactive region. This separation allows the assertion evaluation to complete promptly during the active region while the reporting is deferred to the reactive region, where power state changes have been detected and handled, thus eliminating race conditions without sacrificing overall simulation efficiency.
Solution Approach 2:
A power state detection mechanism acts as an intermediary between the active region evaluation and reactive region reporting. This intermediary monitors for power state changes and ensures that assertion results are only reported after the correct power domain state is established, preventing race conditions while maintaining efficient simulation flow.
3Measurement precision
If hybrid deferred assertions (HDAs) are used to avoid race conditions, then accurate and granular reporting is achieved, but the conversion process from SIAs to HDAs increases complexity
Solution Approach 1:
The system applies different evaluation and reporting characteristics to different regions of the simulation cycle: the active region performs immediate evaluation with power state detection, while the reactive region performs deferred reporting. This local differentiation allows precise, granular reporting without requiring complete conversion of all assertions to complex HDAs, as the precision is achieved through the regional differentiation of evaluation and reporting phases.
Data Source
AI summary
A logic simulation electronic design automation (EDA) application, the logic can be configured to receive a circuit design of an integrated circuit (IC) chip, the circuit design comprising an imported module comprising a list of simple immediate assertions (SIAs) for the imported module, wherein the circuit design comprises a first power domain and a second power domain, wherein the first power domain controls a power state of the second power domain and the imported module is assigned to the second power domain. The logic simulation EDA application can be configured to convert, in response to user input, each SIA in the list of SIAs into a respective hybrid deferred assertion (HDA) to form a list of HDAs for the imported module and execute a simulation of the IC chip, and execution of the simulation can include execution of a plurality of time slots for a plurality of simulation cycles.