Hybrid Digital Delay Beamforming with Partial-Beam True Time Delay
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Solution Overview
Problem
Conventional RF signal processing in communication devices requires multiple time delay circuits for each antenna/beam combination, leading to high power consumption due to numerous multiply operations.
Innovation Solution
Hybrid digital delay beamforming circuits apply a single phasor multiplication operation and true time delay only to partially formed beams at the output of each partial beamforming network, reducing the number of multiply operations and overall power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple time delay circuits are implemented for each antenna/beam combination, then timing accuracy is improved, but power consumption increases due to numerous multiply operations
Solution Approach 1:
The beamforming process is segmented into partial beamforming networks that process antenna signals separately, followed by a single TTD circuit that applies time delay to the partially formed beams. This segmentation reduces the number of TTD operations from multiple per antenna/beam combination to a single operation per partial beam, significantly reducing power consumption while maintaining timing accuracy.
Solution Approach 2:
The invention applies time delay only to partially formed beams rather than to every antenna/beam combination. By performing partial beamforming first and then applying TTD once per partial beam, the system performs sufficient delay correction without the excessive multiply operations of conventional approaches, reducing power consumption while achieving the required timing precision.
2Measurement precision
If conventional time delay circuits with multiple multiply operations are used for each antenna/beam combination, then timing offset compensation is improved, but processing complexity increases
Solution Approach 1:
The signal processing is divided into partial beamforming stages followed by a single TTD stage. This segmentation transforms the complex task of applying multiple individual delays into a simpler two-stage process: partial beamforming followed by one delay operation per partial beam, reducing overall processing complexity while maintaining timing offset compensation accuracy.
Solution Approach 2:
Multiple partial beam signals are merged/combined into fully formed beams after the TTD operation. By performing partial beamforming separately and then combining the results with a single TTD application per partial beam, the system reduces processing complexity compared to applying individual delays to each antenna/beam combination before combining.
3Use of energy by moving object
If a single phasor multiplication operation is applied to partially formed beams, then power consumption is reduced, but beamforming accuracy must be maintained
Solution Approach 1:
Partial beamforming is performed as a preliminary action before applying the single TTD operation. By pre-processing the antenna signals through partial beamforming networks, the system prepares the signals in a form that requires only one subsequent delay operation per partial beam, reducing power consumption while maintaining the accuracy needed for precise beamforming through the phasor multiplication.
Data Source
AI summary
An integrated circuit may include a phase shifting/partial beamforming network circuit and a plurality of true time delay (TTD) circuits. The beamforming circuit may include a plurality of receive inputs. Each receive input may be coupled to one of a plurality of antenna elements. The beamforming circuit may include a plurality of receive/transmit connectors, each of which may correspond to a beam of a plurality of beams. The beamforming circuit may include a plurality of transmit outputs each of which may be coupled to one of the plurality of antenna elements. Each TTD circuit may include a first connection coupled to one of the receive/transmit connector outputs and a second connection coupled to one of a plurality of serial lines. Each TTD circuit may be configured to apply one or more of an integer delay or a fractional delay to data received from the receive/transmit connector or the serial line.