Hybrid Digital Delay Line Clocking for Glitch-Free Code Updates
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Solution Overview
Problem
Existing clocking schemes for memory interfaces, such as LPDDR5, face issues with glitches during on-the-fly updates of delay line codes due to voltage and temperature changes, leading to data corruption and increased complexity in clock gating and sequencing operations.
Innovation Solution
A hybrid digital delay line system using a single path digitally controlled coarse delay line with anti-aging circuitry and dual path coarse delay line, enabling glitch-free on-the-fly updates by alternating clock paths and fine delay code switching to maintain delay consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a single path digitally controlled coarse delay line is used for on-the-fly updates, then power consumption and area are reduced, but glitches occur during delay line code updates
Solution Approach 1:
The patent enables the forward path before disabling the return path, performing the enabling action in advance to prevent glitches during the transition. This preliminary action ensures that the clock signal path is already established before the old path is disconnected, eliminating harmful transient effects.
Solution Approach 2:
The patent dynamically switches between forward and return paths using digitally controlled switches that respond to update signals. This dynamic switching allows the delay line to adapt its configuration in real-time while maintaining continuous, glitch-free operation through controlled transitions.
2Area of stationary object
If a single path digitally controlled coarse delay line is used, then area is reduced by 30%, but complexity in clock gating and sequencing operations increases
Solution Approach 1:
The patent extracts and eliminates the return path from the traditional dual-path delay line configuration, retaining only the forward path with digitally controlled switches. This extraction reduces the circuit area while the control logic manages the simplified single-path configuration to reduce sequencing complexity.
Solution Approach 2:
The single path delay line structure serves multiple functions: it provides delay adjustment, enables glitch-free updates, and reduces area. The digitally controlled switches perform both signal routing and delay adjustment functions, consolidating multiple roles into a universal structure.
3Stability of the object's composition
If delay line codes are updated on-the-fly to compensate for voltage and temperature changes, then clocking stability is improved, but glitches cause data corruption
Solution Approach 1:
The forward path is enabled before the return path is disabled during delay line code updates. This preliminary enabling ensures that the clock signal has already established its new path before the old path is disconnected, preventing glitches that would otherwise corrupt data while maintaining clocking stability.
4Reliability
If a hybrid dual path coarse delay line is used instead of single path, then glitch-free operation is achieved, but power consumption and area increase
Solution Approach 1:
By enabling the forward path before disabling the return path, the patent achieves glitch-free operation in a single-path configuration, eliminating the need for a hybrid dual-path structure. This preliminary action maintains reliability while avoiding the increased power consumption and area that would result from implementing a dual-path system.
Data Source
AI summary
A high-speed clocking circuit may include a single path digitally controlled coarse delay line including multiple stages. Each of the multiple stages may include a plurality of inverters and a logic gate electrically connected in series that are configured to enable a forward path of the single path digitally controlled coarse delay line prior to disabling a return path of the single path digitally controlled coarse delay line to minimize glitching.