Hybrid Delay Model Circuit for Accurate Low-Power Timing
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Solution Overview
Problem
Accurate delay models in integrated circuits consume high power, while low power models are less accurate due to process, temperature, and voltage variations, and cannot be dynamically adjusted once manufactured.
Innovation Solution
A hybrid delay model circuit comprising an accurate delay model and a low power delay model, where the low power model is adjusted by a compare circuit to match the accurate model's accuracy, and a switching circuit to conserve power by switching between the two models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an accurate delay model using full size gates and wires is used, then modeling accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic switching between accurate and low power delay models based on operational requirements. A controller selectively activates either the full-size accurate model or the scaled-down low power model, allowing the system to adapt its power consumption and accuracy characteristics in real-time based on the specific application context.
Solution Approach 2:
The patent changes physical parameters of the delay model by using different gate sizes and wire dimensions. The low power model employs minimum size gates and wires compared to the full size gates and wires in the accurate model, thereby reducing power consumption while maintaining functional equivalence for delay modeling purposes.
2Use of energy by moving object
If a low power delay model with smaller gates and wires is used, then power consumption is reduced, but modeling accuracy deteriorates
Solution Approach 1:
The system dynamically selects between low power and accurate models based on operational context. When high precision is not required, the low power model with minimum size gates and wires is activated to conserve energy. When high accuracy is needed, the system switches to the full-size accurate model, thus optimizing the trade-off between power consumption and modeling precision.
Solution Approach 2:
The patent introduces a controller as an intermediary that manages the selection and switching between different delay model implementations. This controller acts as a mediator that determines which model (low power or accurate) should be active based on system requirements, thereby协调 the trade-off between power consumption and accuracy.
3Measurement precision
If static adjustment is applied to low power delay models during design, then modeling accuracy is improved for specific conditions, but adaptability to dynamic environmental changes is lost
Solution Approach 1:
The patent transforms the static adjustment approach into a dynamic system by implementing real-time switching between pre-characterized delay models. The controller monitors operational conditions and selectively activates the appropriate model (low power or accurate) based on current temperature, voltage, and process conditions, thereby maintaining accuracy across varying environmental conditions without requiring continuous retuning.
Solution Approach 2:
The patent applies preliminary characterization and tuning to multiple delay models during the design phase. Both the low power model and the accurate model are pre-adjusted for different operating conditions. This preliminary action enables the runtime controller to select the most appropriate pre-tuned model for current conditions, avoiding the need for dynamic retuning while maintaining adaptability.
Data Source
AI summary
Circuits, apparatuses, and methods are disclosed for delay models. In one such example circuit, a first delay model circuit is configured to provide a first output signal by modeling a delay of a signal through a path. A second delay model circuit is configured to provide a second output signal by modeling the delay of the signal through the path. A compare circuit is coupled to the first and second delay model circuits. The compare circuit is configured to compare a third signal from the first delay model circuit and a fourth signal from the second delay model circuit, and, in response provide an adjustment signal to adjust the delay of the second delay model circuit.