Hybrid DFE Synchronization for Flexible Low-Power DPD Adaptation

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Solution Overview

Problem

Existing digital front end (DFE) radio systems face inefficiencies due to the trade-off between flexibility and efficiency, with programmable processing arrays being computationally intensive and costly, while hardwired ASIC solutions lack flexibility and adaptability.

Innovation Solution

A hybrid architecture combining programmable processing arrays and hardwired hardware accelerators, optimizing flexibility and efficiency by performing certain DFE functions in dedicated hardware blocks and adapting DPD parameters in software, with synchronized data processing across components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If programmable processing arrays are used for DFE computations, then flexibility and adaptability are improved, but processing power consumption and cost increase

Engineering Contradiction:

ImproveflexibilityVSAvoidprocessing power consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The system divides DFE computations into two segments: time-aligned DPD parameter adaptation computations performed in the programmable processing array, and application of DPD terms to data samples performed in hardwired hardware blocks. This segmentation allows each component to perform only its specialized function, reducing the overall processing power requirements while maintaining flexibility in the adaptation stage.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system dynamically adapts DPD parameters in the programmable processing array based on time-aligned data samples, then applies these parameters in hardware blocks. This dynamic adaptation approach allows the system to maintain flexibility for different communication conditions while using efficient hardware for the repetitive application phase, reducing overall power consumption.

Inventive Principle:

Principle #15Dynamics

2Use of energy by moving object

If hardwired ASIC solutions are implemented, then processing efficiency and power consumption are improved, but flexibility and adaptability are reduced

Engineering Contradiction:

Improvepower consumptionVSAvoidflexibility

Core Design Contradiction:

Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The system segments the DFE functionality into adaptable parameter adaptation (in programmable array) and efficient term application (in hardwired blocks). This allows the hardwired portion to handle the power-intensive repetitive operations efficiently, while the programmable portion provides necessary flexibility for adaptation, achieving a balance between power efficiency and adaptability.

Inventive Principle:

Principle #1Segmentation

3Adaptability or versatility

If hybrid systems combine hardware accelerators and programmable arrays, then a balance between flexibility and efficiency is achieved, but device complexity increases

Engineering Contradiction:

ImproveflexibilityVSAvoidsystem complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The hybrid system is segmented into distinct functional blocks with clearly defined interfaces: the programmable processing array handles DPD parameter adaptation, while hardwired hardware blocks handle application of DPD terms. This clear segmentation simplifies the overall system architecture by assigning specific responsibilities to each component, reducing the complexity that would arise from a fully integrated design.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system performs preliminary time-alignment of data samples before they are used for DPD parameter adaptation. This preliminary action ensures that the data is properly synchronized and formatted before entering the hybrid processing pipeline, simplifying the subsequent processing stages and reducing the complexity of coordination between hardware components.

Inventive Principle:

Principle #10Preliminary action

4Measurement precision

If time-aligned data samples are provided to processing array, then measurement precision for DPD computation is improved, but data processing time and synchronization complexity increase

Engineering Contradiction:

ImproveDPD parameter accuracyVSAvoidsynchronization overhead

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The system performs preliminary time-alignment of data samples using buffer memory and control logic before they are provided to the processing array for DPD computation. This preliminary action ensures that the data samples are properly synchronized in time, improving the accuracy of DPD parameter adaptation, while the efficient buffer management minimizes the time overhead associated with synchronization.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12490272B2Data synchronization techniques for a hybrid hardware accelerator and programmable processing array architecture

Publication Date: 2025.12.02 INTEL CORP

AI summary

Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted and a measured or observed transmission of the data samples. By comparing these blocks of data samples, DFE functions such as digital pre-distortion (DPD) parameter adaptation may be implemented. The hybrid architecture enables high flexibility at low additional cost. To further limit the costs, the programable processing array may have processing power and memory that is reduced compared to conventional processing array implementations.