Hybrid Die Interconnect Assembly Without Intermediate RDL
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Solution Overview
Problem
Conventional multi-die IC packages face challenges in achieving high interconnect density due to increased die stacking, leading to costly manufacturing operations, mechanical stress from material mismatch, and reduced reliability due to thermal expansion differences and power drop across intermediate redistribution layers.
Innovation Solution
A microelectronic assembly design featuring a first die with a redistribution layer coupled via non-solder interconnects and a second die directly soldered to the first die, eliminating the need for an intermediate redistribution layer, which reduces manufacturing complexity and enhances signal integrity by using continuous insulating material around the dies and interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an intermediate redistribution layer is used to couple dies, then interconnect density can be achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent removes the intermediate redistribution layer from the multi-die package structure, directly coupling dies together without the additional RDL layer. This extraction of the unnecessary component simplifies the manufacturing process while maintaining interconnect density through direct die-to-die bonding with solder bumps.
Solution Approach 2:
The patent segments the interconnect function into direct solder bump connections between dies, eliminating the need for a continuous RDL structure. Each die maintains its own pad structure, and interconnects are formed through discrete solder bumps that directly bridge adjacent dies, simplifying the overall manufacturing complexity.
2Adaptability or versatility
If an intermediate redistribution layer is used, then routing flexibility is improved, but mechanical stress from material mismatch increases
Solution Approach 1:
By removing the intermediate RDL layer, the patent eliminates the material interface between the RDL substrate and die materials. This reduces the number of dissimilar materials in thermal and mechanical contact, thereby minimizing stress accumulation from coefficient of thermal expansion (CTE) mismatch during temperature cycling.
Solution Approach 2:
The patent creates a more homogeneous material structure by directly bonding dies together with solder, reducing the material heterogeneity that would exist with an intermediate RDL layer. The solder interconnect provides a metallurgical bond that is more compatible with both die substrates, reducing mechanical stress.
3Adaptability or versatility
If an intermediate redistribution layer is used, then signal routing is improved, but power drop increases
Solution Approach 1:
The patent removes the intermediate RDL layer that acts as an additional resistance path for power delivery. By enabling direct die-to-die connections, power and signal currents travel through shorter, lower-resistance solder bump interconnects rather than having to route through the RDL conductors, thereby reducing I²R power losses.
Solution Approach 2:
The patent transitions from planar routing through an RDL to vertical/stacked routing through solder bumps. This dimensional change allows power and signal paths to be established through the thickness of the die stack rather than laterally through the RDL plane, significantly shortening current paths and reducing power drop.
4Manufacturing precision
If dies are directly stacked, then interconnect density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses identical or matched pad patterns on adjacent dies that serve as alignment references during bonding. The solder bumps are formed with dimensions and spacing that replicate the pad geometry, providing self-aligning features that simplify the bonding process and reduce the stringency of alignment precision requirements during die stacking.
Solution Approach 2:
The patent employs underfill material applied before or during the die bonding process to compensate for minor misalignments between dies. The underfill flows into gaps and provides mechanical support, cushioning against the effects of alignment errors and preventing stress concentration that would occur with perfect rigid alignment, thereby tolerating lower alignment precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design increases interconnect density, reduces routing distances, and improves signal and power integrity while minimizing manufacturing costs and mechanical stress, offering greater flexibility for electronics designers and manufacturers.
Implementation Method 1
a second die at the second surface of the first die, wherein the second die is electrically coupled directly to the second surface of the first die by solder interconnects
Implementation Method 2
the first surface of the first die is on and electrically coupled to the surface of the RDL by non-solder interconnects
Data Source
AI summary
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface; a redistribution layer (RDL) having a surface, wherein the first surface of the first die is on and electrically coupled to the surface of the RDL by non-solder interconnects; and a second die at the second surface of the first die, wherein the second die is electrically coupled directly to the second surface of the first die by solder interconnects.