Hybrid-Bonded Die Stack Packaging for Thin 3D Thermal Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and efficient thermal dissipation in semiconductor packages due to limitations in current packaging techniques, particularly in Package-on-Package (PoP) technology, which struggles with reducing package thickness and enhancing thermal management while maintaining electrical performance.
Innovation Solution
The solution involves hybrid bonding of stacked semiconductor dies with through vias and thermal vias within an encapsulant, allowing for reduced thickness and increased density, along with a redistribution structure for electrical connectivity, enabling improved thermal dissipation and signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Package-on-Package (PoP) technology is used to increase integration density, then component density is improved, but package thickness cannot be sufficiently reduced
Solution Approach 1:
The patent transitions from planar side-by-side packaging to three-dimensional stacked packaging, where semiconductor dies are vertically stacked and bonded together. This dimensional change allows multiple components to occupy the same footprint area while reducing the overall package thickness compared to traditional PoP architectures.
Solution Approach 2:
The patent implements a nested structure where smaller semiconductor dies are stacked and bonded within a compact footprint, similar to nested dolls. Multiple functional layers are integrated vertically, with each die nested within the overall package structure, maximizing space utilization and reducing thickness.
2Ease of manufacture
If conventional packaging techniques are used, then manufacturing is simpler, but thermal dissipation is insufficient
Solution Approach 1:
The patent introduces thermal interface materials and thermally conductive structures as intermediaries between the semiconductor dies and the package substrate. These intermediary elements facilitate efficient heat transfer from the high-density stacked dies to the cooling structures, solving the thermal dissipation problem while maintaining the compact stacked architecture.
Solution Approach 2:
The patent utilizes thermally conductive materials with appropriate thermal expansion coefficients that match the semiconductor dies and substrate. This ensures efficient thermal conduction while accommodating thermal expansion during operation, preventing delamination and maintaining thermal pathways in the high-density stacked package.
3Quantity of substance
If die stacking is increased to improve density, then integration level is improved, but electrical performance may deteriorate
Solution Approach 1:
The patent replaces traditional mechanical wire bonding with direct die-to-die bonding and through-silicon via (TSV) interconnections. This substitution eliminates the mechanical complexity and signal degradation associated with wire bonds, providing shorter, more reliable electrical pathways that maintain high-speed signal integrity in densely stacked configurations.
Solution Approach 2:
The patent transitions electrical interconnections from lateral routing to vertical routing through the use of through-silicon vias and direct bonding interfaces. This dimensional change in signal pathways reduces interconnection length and parasitic effects, maintaining electrical performance despite increased stacking density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in cost savings by identifying faulty chips early, enhancing thermal dissipation, allowing for flexible die stacking, and improving signal transmission performance, while integrating well with wafer-to-wafer bonding processes for manufacturing efficiency.
Implementation Method 1
hybrid bonding of stacked semiconductor dies with through vias and thermal vias within an encapsulant
Implementation Method 2
a plurality of thermal vias extending through the encapsulant, wherein the plurality of thermal vias are disposed on a surface of the second die and adjacent the first die
Data Source
AI summary
A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.