Hybrid Die Stacking With TSVs for Reliable Sub-25 μm Interconnects
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Solution Overview
Problem
The existing solder-based interconnects face technical challenges, such as failures and faults, at interconnect pitches below 25 μm, and there is a need to integrate hybrid bonding interconnect (HBI) components with solder-attach components to achieve high wiring density and scale the interconnect pitch downward.
Innovation Solution
The proposed solution involves creating a hybrid solder and solderless die stacking architecture by forming a HBI die complex with two or more semiconductor dies and stacking a solder-attach component, such as DRAM or HBM, on the HBI die complex, using through silicon vias (TSVs) and a die-to-die physical interface (D2D PHY) to facilitate electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If solder-based interconnects are used to achieve high wiring density, then interconnect pitch can be reduced, but reliability deteriorates with pitches below 25 μm due to failures and faults
Solution Approach 1:
The patent segments the interconnect system into two distinct parts: solder-based interconnects for pitches of 25 μm and above, and hybrid bonding interconnects for pitches below 25 μm. This segmentation allows each technology to operate in its optimal range, with solder providing robust connections for larger pitches and hybrid bonding enabling reliable sub-25 μm pitches through direct metal-to-metal bonding without solder
Solution Approach 2:
The patent introduces an intermediary approach by creating a hybrid bonding system that uses direct metal-to-metal bonding as a mediator between die structures. This intermediary bonding mechanism eliminates the need for solder in sub-25 μm pitch applications, providing a reliable connection method that bridges the gap where traditional soldering fails
2Manufacturing precision
If hybrid bonding interconnects are used to scale interconnect pitch downward below 25 μm, then wiring density improves, but device complexity increases due to integration challenges with solder-attach components
Solution Approach 1:
The patent applies local quality by assigning different bonding technologies to different spatial locations and functional requirements within the same device architecture. Solder-attach components are used where larger pitches and traditional bonding are sufficient, while hybrid bonding is applied specifically in regions requiring sub-25 μm pitch. This localized application of different bonding qualities simplifies the overall integration challenge by matching technology to specific functional needs rather than requiring a single complex solution throughout
Solution Approach 2:
The patent creates a universal bonding architecture that can accommodate both solder-based and hybrid bonding interconnects within the same device structure. The system is designed to be multi-functional, supporting both bonding methodologies and allowing seamless integration of components with different pitch requirements. This universality reduces device complexity by providing a flexible platform that handles diverse interconnect requirements through a unified architectural framework
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient hybrid solder and solderless die stacking, reducing the size and interconnect length, improving performance, and overcoming the limitations of solder-based interconnects at small pitches.
Implementation Method 1
Hybrid bonding, also called direct bond interconnect (DBI) is a packaging technology that involves bringing together the surfaces of two semiconductor devices under applied pressure and/or at elevated temperature, generally as a die stacking solution, resulting in dielectric-to-dielectric bonding and metal-to-metal bonding
Implementation Method 2
the solder-attach component, such as a dynamic random access memory (DRAM) component or a high bandwidth memory (HBM) component, is then soldered to the semiconductor die
Data Source
AI summary
Methods and architectures for hybrid solder and solderless die stacking. Devices include a semiconductor die that is solderless bonded (using hybrid bonding interconnect (HBI) technology) at a bottom surface to a base die. The semiconductor die includes a region with through silicon vias (TSVs) exposed at an upper surface. The semiconductor die and the TSVs are configured to have a solder-attach component, such as a DRAM or high bandwidth memory (HBM), attached thereto. The solder-attach component is stacked on the semiconductor die and soldered to the semiconductor die at the TSVs.