Hybrid DIMM Caching with DRAM and 3D Cross-Point Memory
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Solution Overview
Problem
Conventional memory sub-systems face performance issues due to differences in interface protocols and data access granularities between DRAM and 3D cross-point memory, leading to high traffic and reduced performance when used together, and challenges in tracking data access patterns for effective caching.
Innovation Solution
A hybrid dual in-line memory module (DIMM) that uses DRAM as a low-latency cache for 3D cross-point memory, with a controller managing data access patterns to select which data to store in DRAM for faster access, thereby reducing latency and increasing capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM and 3D cross-point memory are used together in a hybrid DIMM, then capacity is increased, but interface protocol differences cause high traffic and reduced performance
Solution Approach 1:
The patent introduces a buffer memory component as an intermediary between DRAM and 3D cross-point memory. This buffer acts as a mediator that translates between different interface protocols and data access granularities, allowing the two memory types to communicate efficiently without direct protocol conflicts, thereby resolving the performance degradation caused by interface incompatibility
2Quantity of substance
If DRAM and 3D cross-point memory are used together in a hybrid DIMM, then capacity is increased, but data access granularity differences cause high traffic
Solution Approach 1:
The patent segments data access operations into different granularity levels appropriate for each memory type. The buffer memory divides data into units that match the native access granularity of 3D cross-point memory, allowing efficient bulk transfers while maintaining the fine-grained access capabilities of DRAM, thereby reducing unnecessary data traffic overhead
3Loss of time
If caching is implemented in hybrid DIMM, then data access latency is reduced, but tracking data access patterns becomes complex
Solution Approach 1:
The buffer memory component autonomously tracks data access patterns and autonomously decides which data to cache in DRAM without requiring complex external control logic. The buffer monitors access frequencies and patterns, automatically identifying hot data that should be cached, thereby reducing data access latency while keeping the control mechanism relatively simple
Data Source
AI summary
A system includes a first memory device of a first memory type, a second memory device of a second memory type, and a third memory device of a third memory type. The system further includes a processing device to retrieve one or more sections of data from the first memory device comprising a first memory type, and retrieve one or more remaining sections of data from the second memory device comprising a second memory type, wherein the one or more remaining sections of data from the second memory device are associated with the one or more sections of data from the first memory device. The processing device is further to combine the one or more sections of data from the first memory device comprising the first memory type with the one or more remaining sections of each of data from the second memory device comprising the second memory type into a contiguous page, and copy the contiguous page to a third memory device comprising a third memory type.