Hybrid DLL Delay Cell for Low Jitter at Low Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Delay-cell jitter is a significant limiting factor for achieving high data rates in Delay Locked Loop (DLL) based serial link designs, primarily due to CMOS transistor channel thermal noise, and current solutions that reduce jitter increase power consumption.
Innovation Solution
A hybrid delay cell combining a resistive digital-to-analog converter (R-DAC) first stage with a current-starved delay cell second stage, utilizing pFET and nFET transistors, provides low jitter and configurable delay generation at low power, optimizing performance through coarse and fine tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If more current is burned in the devices to reduce jitter, then jitter performance is improved, but power consumption increases
Solution Approach 1:
The delay cell is divided into two distinct stages: a first stage using an RDAC with pFET and nFET for low-jitter delay generation, and a second stage using a current-starved delay cell for configurable delay. This segmentation allows each stage to optimize for its specific function, with the first stage providing low jitter performance and the second stage providing power-efficient delay control.
Solution Approach 2:
The patent combines two different delay cell topologies (RDAC-based and current-starved) into a single hybrid structure. The RDAC stage provides inherent lower jitter performance while the current-starved stage provides area-efficient delay configurability, achieving both low jitter and low power consumption simultaneously.
2Use of energy by moving object
If conventional current-starved delay cells are used, then power consumption is reduced, but jitter performance deteriorates
Solution Approach 1:
The delay cell is divided into two distinct stages: a first stage using an RDAC with pFET and nFET for low-jitter delay generation, and a second stage using a current-starved delay cell for configurable delay. This segmentation allows each stage to optimize for its specific function, with the first stage providing low jitter performance and the second stage providing power-efficient delay control.
Solution Approach 2:
The patent combines two different delay cell topologies (RDAC-based and current-starved) into a single hybrid structure. The RDAC stage provides inherent lower jitter performance while the current-starved stage provides area-efficient delay configurability, achieving both low jitter and low power consumption simultaneously.
3Adaptability or versatility
If delay configurability is increased, then adaptability is improved, but device complexity increases
Solution Approach 1:
The delay cell is divided into two distinct stages: a first stage using an RDAC with pFET and nFET for low-jitter delay generation, and a second stage using a current-starved delay cell for configurable delay. This segmentation allows each stage to optimize for its specific function, with the first stage providing low jitter performance and the second stage providing power-efficient delay control.
Solution Approach 2:
The current-starved delay cell stage incorporates dynamic control through current starvation mechanisms, allowing the delay to be adjusted by controlling the current flow through the delay elements. This enables configurable delay adjustment without requiring complex additional circuitry.
Data Source
AI summary
A delay cell for a delay locked loop, DLL, based serial link is disclosed. The delay cell has a first stage and a second stage, wherein an output of the first stage is an input to the second stage, the first stage comprising a resistive digital to analog converter, R-DAC and the second stage comprising a current starved delay cell.