Hybrid DLL Delay Circuit for Stable High-Frequency Timing
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Solution Overview
Problem
Conventional delay circuits in semiconductor memory apparatuses face issues with high current consumption, noise, large circuit area, and difficulty in operating at high frequencies due to the use of dual or single delay lines, which result in signal distortion and instability.
Innovation Solution
A hybrid delay circuit design incorporating a first delay circuit unit with a single delay line for input signal delay and a second delay circuit unit with a dual delay line for further signal delay, allowing for flexible control of delay times and operation in both low and high frequencies with reduced noise and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a dual delay line is used in the delay circuit, then the delay time can be adjusted, but the circuit area and current consumption increase
Solution Approach 1:
The patent merges a single delay line and a dual delay line into a hybrid delay circuit. The single delay line provides coarse delay adjustment while the dual delay line provides fine delay adjustment, combining the advantages of both configurations to achieve adjustable delay time with reduced circuit area compared to using only a dual delay line.
Solution Approach 2:
The delay circuit is segmented into two functional units: a first delay circuit unit with a single delay line for coarse adjustment, and a second delay circuit unit with a dual delay line for fine adjustment. This segmentation allows each unit to be optimized for its specific function, reducing the overall circuit area while maintaining delay adjustment capability.
2Area of stationary object
If a single delay line is used in the delay circuit, then the circuit area is reduced, but signal distortion increases and high-frequency operation becomes difficult
Solution Approach 1:
The patent combines a single delay line and a dual delay line in a hybrid configuration. The single delay line handles the majority of the delay requirement with minimal area, while the dual delay line provides additional signal paths that reduce distortion and improve high-frequency performance, thus maintaining signal stability without significantly increasing area.
Solution Approach 2:
Different parts of the delay circuit have different structural qualities: the first delay circuit unit uses a single delay line configuration optimized for area efficiency, while the second delay circuit unit uses a dual delay line configuration optimized for signal quality. This local differentiation allows the circuit to achieve both area efficiency and signal stability.
3Ease of operation
If a driving circuit is added to drive signals on two delay lines, then the delay circuit can operate, but current consumption and noise increase
Solution Approach 1:
The patent merges the driving functions for the single and dual delay lines into a shared control structure. Control signals are generated once and distributed to both delay line units, eliminating the need for separate driving circuits and reducing overall current consumption while maintaining full operability of the hybrid delay circuit.
4Adaptability or versatility
If multiple switches are used to control delayer outputs in a single delay line circuit, then delay time can be adjusted, but the number of switches increases circuit area and reduces stability
Solution Approach 1:
The patent segments the delay control function between two units: the first delay circuit unit uses fewer switches for coarse delay control, while the second delay circuit unit uses even fewer switches for fine delay control. This segmentation reduces the total number of switches required compared to using a single delay line with full adjustment capability.
Solution Approach 2:
The control mechanisms of both delay circuit units are merged under a unified control structure that coordinates the switches in both units. This merging allows the system to achieve fine-grained delay control with fewer total switches by utilizing the complementary strengths of both delay line configurations.
Data Source
AI summary
A delay circuit in a delay locked loop includes a first delay circuit unit for delaying an input signal using a single delay line in response to first control signals and then outputting a first delay signal and a second delay signal, and a second delay circuit unit for delaying the first delay signal and the second delay signal by delay time, which is correspondent to second control signals and third control signals, using a dual delay line and then outputting a third delay signal and a fourth delay signal.