Hybrid Analog-Digital DLL with Fast Open-Loop Digital Locking
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Solution Overview
Problem
Conventional Delay Locked Loops (DLLs) in semiconductor memory devices require a significant number of clock cycles for digital locking and can experience unstable locking conditions due to their closed loop architecture, which slows down the initial locking process and may lead to inaccuracies in phase alignment.
Innovation Solution
A hybrid analog/digital delay locked loop with a configurable architecture that employs an open loop configuration for digital locking, using a hybrid delay line with analog and digital stages, allowing for rapid selection of tap outputs to achieve alignment, followed by a closed loop configuration for fine-tuning with voltage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a closed loop architecture is used for digital locking in DLL, then phase alignment accuracy can be achieved through iterative adjustment, but the locking time increases significantly and stability deteriorates due to the sequential nature of single-stage adjustments per clock cycle
Solution Approach 1:
The patent applies preliminary action by performing coarse digital locking in an open-loop configuration before entering closed-loop analog fine-tuning. The digital delay line stages are pre-configured to achieve approximate phase alignment rapidly, establishing an initial locked condition that enables subsequent precise analog adjustment without the time penalty of iterative digital adjustments.
Solution Approach 2:
The patent segments the locking process into two distinct phases: a first phase using digital delay line stages for coarse locking, and a second phase using analog delay elements for fine-tuning. This segmentation allows each phase to optimize for its specific function - digital for speed and analog for precision - thereby resolving the contradiction between locking time and phase alignment accuracy.
2Productivity
If digital delay line stages are used with closed loop architecture, then delay adjustment can be made in discrete steps, but the resolution and fine-tuning capability are insufficient compared to analog delay lines
Solution Approach 1:
The delay line is segmented into digital delay stages and analog delay elements, with each segment optimized for specific functions. Digital stages provide coarse delay adjustment with high speed, while analog elements provide fine-grained delay resolution. This segmentation resolves the contradiction by allowing the system to leverage the speed advantage of digital stages while maintaining the precision advantage of analog elements.
Solution Approach 2:
Different portions of the delay line have different qualities - digital portions for rapid coarse adjustment and analog portions for precise fine-tuning. The system transitions from digital to analog control as locking progresses, with each portion performing its specialized function optimally. This local quality differentiation resolves the contradiction between adjustment speed and delay resolution.
3Adaptability or versatility
If the maximum number of delay stages is increased to cover the full clock period adjustment range, then the DLL can lock at lower frequencies, but the delay line becomes longer and the locking process becomes more complex and unstable
Solution Approach 1:
The open-loop digital locking phase performs preliminary action by rapidly establishing a locked condition with a limited number of digital stages, covering the necessary frequency range without requiring the full clock period adjustment range. This preliminary locking enables the subsequent analog fine-tuning phase to complete the adjustment with minimal stages, thereby reducing overall complexity while maintaining frequency adaptability.
Solution Approach 2:
The patent extracts the coarse adjustment function to a separate digital delay line stage configuration phase, removing the burden from the analog delay line. By taking out the large-scale adjustment requirement and handling it digitally in open-loop, the analog portion only needs to handle fine-tuning, reducing the required number of analog stages and overall system complexity while preserving frequency range coverage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the digital locking time and enhances the stability of the locking process by allowing rapid adjustment of delay stages, ensuring precise alignment with minimal error, thus improving the overall performance of DLLs in DRAM devices.
Implementation Method 1
a phase detector is utilized to compare the rising edges of a buffered system clock with a feedback signal
Implementation Method 2
voltage-controlled delay elements or delay lines... whose delay is changed by varying a control voltage
Implementation Method 3
digital delay line and utilizes a variable number of individual delay elements whose delay is fixed... and the number of delay elements is digitally varied
Data Source
AI summary
A configurable architecture, hybrid analog/digital delay locked loop and technique with fast open loop digital locking for integrated circuit dynamic random access memory (DRAM) devices and devices incorporating embedded DRAM. The DLL design and technique disclosed employs a hybrid analog/digital delay line, but does not use conventional closed loop architecture during the digital phase of the locking process.