Hybrid Double Patterning for Semiconductor IC Layout Decomposition
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down IC manufacturing due to limitations in traditional double patterning methods, which struggle to produce small feature sizes and are costly, as they require the same resolution in both lithography processes, limiting the minimum critical dimension that can be achieved.
Innovation Solution
The implementation of hybrid double patterning methods, which decompose IC layouts into two subsets suitable for different lithography techniques, such as EUV and 193 nm immersion lithography, allowing for higher resolution and lower costs by using a combination of high-resolution and lower-resolution lithography processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional double patterning methods are used with the same resolution in both lithography processes, then the manufacturing process is simpler to implement, but the minimum critical dimension that can be produced is limited and cannot achieve smaller feature sizes
Solution Approach 1:
The patent segments the lithography process into two distinct stages with different resolution capabilities. The first lithography process uses higher resolution to form initial patterns, while the second process uses lower resolution to form additional patterns. This segmentation allows each process to be optimized independently, achieving smaller critical dimensions without requiring both processes to maintain the same high resolution, thus reducing overall complexity while improving precision.
Solution Approach 2:
The patent applies local quality by assigning different resolution requirements to different parts of the patterning process. Instead of requiring uniform high resolution across both lithography steps, the method allows the first process to operate at higher resolution for critical features while the second process operates at lower resolution for less critical features. This localized optimization enables achievement of smaller minimum critical dimensions without proportionally increasing the complexity of the entire manufacturing system.
2Manufacturing precision
If traditional double patterning methods are used requiring same resolution in both processes, then the process design is more straightforward, but the cost increases and smaller feature sizes cannot be achieved
Solution Approach 1:
The patent changes the resolution parameter between the two lithography processes rather than maintaining the same resolution in both. The first process operates at higher resolution to create initial patterns, while the second process operates at lower resolution to add additional patterns. This parameter change allows the use of less expensive lower-resolution equipment for the second process, reducing manufacturing costs while still achieving smaller feature sizes through the combined patterning effect.
3Manufacturing precision
If hybrid double patterning with different lithography techniques is implemented, then higher resolution and smaller feature sizes are achieved, but the process complexity increases due to decomposition requirements
Solution Approach 1:
The patent performs preliminary layout decomposition before the actual lithography processes. The IC layout is decomposed into two subsets that are suitable for different lithography techniques, and this decomposition is validated to ensure manufacturability. By performing this complex decomposition action in advance, the actual lithography processes themselves become simpler and more straightforward, reducing the operational complexity during manufacturing while achieving higher resolution results.
Data Source
AI summary
A method of fabricating an integrated circuit (IC) uses a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution. The method includes deriving a graph from an IC layout, the graph having vertices and edges that connect some of the vertices, the vertices representing IC patterns in the IC layout, the edges representing spacing between the IC patterns that are smaller than the second resolution. The method further includes classifying the edges into at least two types, a first type of edges representing spacing that is smaller than the first resolution, a second type of edges representing spacing that is equal to or greater than the first resolution but smaller than the second resolution.