Hybrid DRAM Array with Mixed 1T1C and 3T1C Cells

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Solution Overview

Problem

Dynamic random-access memory (DRAM) arrays face challenges in balancing density and latency, with existing cell structures either offering high density but high latency or low density but fast access times, limiting overall performance.

Innovation Solution

A hybrid DRAM array is designed with mixed subarrays of 1T1C and 3T1C cells, allowing for a high-density slow region and a fast low-capacity region, enabling intelligent memory mapping by the controller to optimize performance based on application needs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If 1T1C cell structure is used, then density is improved, but latency increases

Engineering Contradiction:

Improvememory densityVSAvoidaccess latency

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The memory array is segmented into multiple sub-arrays, where each sub-array can be independently accessed. This allows the memory system to selectively access only the necessary portion of data, reducing the effective access latency while maintaining high density through the 1T1C structure in other regions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of organization by creating multiple independent sub-arrays within the memory device. This dimensional expansion allows parallel access to different sub-arrays, effectively reducing latency without compromising the high density achieved through 1T1C cells.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Speed

If 3T1C cell structure is used, then access speed is improved, but density decreases

Engineering Contradiction:

Improveread access speedVSAvoidmemory density

Core Design Contradiction:

SpeedVSQuantity of substance

Solution Approach 1:

Different sub-arrays within the memory device can have different cell structures optimized for their specific function. Sub-arrays requiring fast access can use 3T1C cells, while sub-arrays prioritizing density can use 1T1C cells, allowing each local region to have the quality needed for its purpose.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The memory system dynamically selects which sub-array to access based on the specific data access pattern and performance requirements. This dynamic selection allows the system to optimize between speed and density on a per-access basis rather than being constrained by a fixed cell structure.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS10223252B2Hybrid DRAM array including dissimilar memory cells

Publication Date: 2019.03.05 SAMSUNG ELECTRONICS CO LTD

AI summary

A hybrid memory includes a plurality of tiles including a plurality of rows including a first row having a first type of memory cells and a second row having a second type of memory cells; a pair of bitline select signals including a bitline select signal and a bitline select bar signal that is an inverse of the bitline select signal; a wordline driver that is configured to receive an input data; a sense amplifier that is configured to output an output data; a write bitline coupled to the first row and the second row; a read bitline coupled to the first row and the second row; a wordline coupled to each of the plurality of rows; and a bitline that is coupled to the write bitline and the read bitline based on set values of the pair of bitline select signals.