Hybrid DRAM-NVM Memory System with OS Page Migration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional DRAM-based main memory systems face challenges with volatility and high write speeds, while non-volatile memory technologies like flash memory offer density and energy efficiency but suffer from write latency and wear-out issues, making it difficult to integrate them effectively in computer systems.
Innovation Solution
A hybrid memory system combining DRAM and non-volatile memory (NVM) like flash or Phase-Change RAM, where DRAM is used for buffering and page migration is managed by the operating system to compensate for the drawbacks of NVM, utilizing DRAM for temporary storage and NVM for long-term data retention, with policies to avoid endurance problems and ensure efficient data migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory (NVM) is used for main memory, then data retention and energy efficiency are improved, but write latency and wear-out issues worsen
Solution Approach 1:
The memory system is segmented into multiple channels, with at least one NVM channel and one DRAM channel. The controller divides write operations into multiple segments, performing write operations to different channels in parallel or sequentially to mask the latency of NVM writes.
Solution Approach 2:
DRAM channels serve as intermediary buffers between the processor and NVM channels. Data is first written to DRAM channels which have lower latency, then asynchronously transferred to NVM channels for permanent storage, mediating between the speed requirements of the processor and the retention requirements of NVM.
2Quantity of substance
If non-volatile memory (NVM) is used for main memory, then density and energy efficiency are improved, but write speed and endurance worsen
Solution Approach 1:
The memory system is segmented into multiple channels, with at least one NVM channel and one DRAM channel. The controller divides write operations into multiple segments, performing write operations to different channels in parallel or sequentially to mask the latency of NVM writes.
Solution Approach 2:
The system performs partial write operations to DRAM channels immediately to satisfy processor speed requirements, while completing the full write to NVM channels asynchronously when time permits, performing more than minimally required actions to maintain both speed and density benefits.
3Speed
If DRAM is used for main memory, then write speed and accessibility are improved, but volatility and energy consumption worsen
Solution Approach 1:
The system merges DRAM and NVM technologies into a unified memory system with multiple channels. DRAM channels provide fast volatile storage while NVM channels provide slow non-volatile storage, combining the advantages of both technologies to achieve both speed and stability.
Solution Approach 2:
The system dynamically selects which channel to write to based on the urgency of the write operation. Time-critical writes go to DRAM channels for immediate completion, while less urgent writes are directed to NVM channels, allowing the system to adapt its behavior to different operational requirements.
Data Source
AI summary
One embodiment is main memory that includes a combination of non-volatile memory (NVM) and dynamic random access memory (DRAM). An operating system migrates data between the NVM and the DRAM.