Hybrid DRAM and SCM Memory Access Control for Power-Speed Trade-off

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Solution Overview

Problem

Computer systems face challenges in achieving high-speed and low-power data processing due to the trade-off between dynamic random access memory (DRAM) and storage class memory (SCM), where DRAM provides fast access but high standby power, while SCM has high integration capacity but slower access speeds.

Innovation Solution

An information processing device that includes a processing circuit, a first memory (DRAM), and a nonvolatile memory, with a managing device that dynamically selects between DRAM and SCM based on operation information to optimize memory access methods, such as first-type and second-type access operations, to balance performance and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If all main memory devices are implemented using DRAM, then processing speed is improved, but standby power consumption increases

Engineering Contradiction:
Improveprocessing speedVSAvoidstandby power consumption
Core Design Contradiction:
SpeedVSUse of energy by stationary object

Solution Approach 1:

The memory system is segmented into multiple memory devices with different characteristics (DRAM and storage class memory). The managing device divides memory management into separate control paths, allowing different memory types to be used for different purposes - DRAM for frequently accessed data requiring fast access, and storage class memory for data where power consumption is more critical.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically selects between different memory control methods based on operational conditions. The managing device monitors memory access patterns and workload characteristics, then adaptively chooses whether to use DRAM-only mode, storage class memory-only mode, or a hybrid approach, optimizing the balance between speed and power consumption in real-time.

Inventive Principle:
Principle #15Dynamics

2Use of energy by stationary object

If all main memory devices are implemented using storage class memory, then standby power consumption is reduced, but processing speed decreases

Engineering Contradiction:
Improvestandby power consumptionVSAvoidprocessing speed
Core Design Contradiction:
Use of energy by stationary objectVSSpeed

Solution Approach 1:

The memory system is segmented into multiple memory devices with different characteristics (DRAM and storage class memory). The managing device divides memory management into separate control paths, allowing different memory types to be used for different purposes - DRAM for frequently accessed data requiring fast access, and storage class memory for data where power consumption is more critical.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically selects between different memory control methods based on operational conditions. The managing device monitors memory access patterns and workload characteristics, then adaptively chooses whether to use DRAM-only mode, storage class memory-only mode, or a hybrid approach, optimizing the balance between speed and power consumption in real-time.

Inventive Principle:
Principle #15Dynamics

3Speed

If a hybrid memory system combining DRAM and storage class memory is used, then both speed and power consumption can be optimized, but memory control complexity increases

Engineering Contradiction:
Improveprocessing speedVSAvoidmemory control complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The managing device automatically monitors memory access patterns, workload characteristics, and system state, then autonomously selects the appropriate memory control method without requiring manual intervention or complex external control logic. The system self-adjusts to optimize performance based on current conditions.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The managing device continuously monitors memory access patterns and system performance, using this feedback to dynamically adjust memory control methods. The system learns from past access patterns and adapts its memory management strategy to predict and optimize for future workloads.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10719247B2Information processing device, information processing method, estimation device, estimation method, and computer program product
Publication Date: 2020.07.21 KK TOSHIBA
  • US10719247B2 patent drawing
  • US10719247B2 patent drawing
  • US10719247B2 patent drawing

AI summary

An information processing device according to an embodiment includes a processing circuit. The processing circuit is configured to: obtains operation information; estimates, based on the obtained operation information, the execution performance of memory accesses with respect to a first memory and a nonvolatile memory unit in the case in which a managing device performs operations according to each of a plurality of memory control methods; selects, based on the execution performance estimated for each memory control method, any one memory control method from among a plurality of memory control methods; and performs a setting operation with respect to an access managing unit in such a way that the managing device accesses the first memory and the nonvolatile memory unit according to the selected memory control method.