Packaged Hybrid E-Mode Transistor for High-Voltage Reliability
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Solution Overview
Problem
The reliable fabrication and manufacturing of high-voltage enhancement-mode (E-mode) III-N semiconductor devices have proven difficult, leading to the use of hybrid devices combining high-voltage depletion-mode (D-mode) and low-voltage E-mode transistors, which require modifications to achieve desired output characteristics.
Innovation Solution
The development of packaged hybrid enhancement-mode electronic components that include a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor within a single package, with configurations such as integrated resistors or specific electrical connections to enhance performance and survivability during high-voltage applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single high-voltage enhancement-mode III-N device is fabricated, then the device can block high voltages and conduct current reliably, but the fabrication and manufacturing have proven very difficult
Solution Approach 1:
The patent divides the single high-voltage enhancement-mode device into two separate transistors: a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. These segmented devices are then combined in a hybrid configuration within a single package, making the device manufacturable while maintaining the desired high-voltage blocking capability and reliable operation.
2Reliability
If a hybrid device combining high-voltage depletion-mode and low-voltage enhancement-mode transistors is used, then the device can achieve high-voltage blocking capability, but modifications are necessary to achieve desired output characteristics
Solution Approach 1:
The patent merges the high-voltage depletion-mode transistor and low-voltage enhancement-mode transistor into a single integrated hybrid device package with unified electrical connections. This combining approach achieves the desired high-voltage blocking capability while providing a standardized structure that reduces the need for external modifications compared to separate discrete devices.
3Reliability
If conventional hybrid device configuration is used, then the device can block high voltages, but current flow and slew rates are not limited, causing electromagnetic interference and potential damage
Solution Approach 1:
The patent incorporates current-limiting resistors and RC snubber circuits into the hybrid device structure before the harmful effects occur. These protective elements are pre-configured to limit current flow and control slew rates, preventing electromagnetic interference and potential damage to the device or external circuitry before they can occur during operation.
Data Source
AI summary
An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.