Hybrid eDRAM-MRAM Bit-Cell for Embedded Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current embedded memory technologies, such as STT-MRAM and eDRAM, face challenges with high voltage and current-density requirements during programming and low retention time due to leakage, respectively, which affect energy and computational efficiency.
Innovation Solution
A hybrid integrated MRAM and eDRAM bit-cell design that uses a Metal-Insulator-Metal (MIM) based capacitor and packs two bit-cells together with at most four control lines, enabling fast write and read performance, long retention time, and high-density packaging by switching between eDRAM and MRAM modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If STT-MRAM is used for embedded memory, then non-volatility is achieved, but high voltage and high current-density problems occur during programming
Solution Approach 1:
The patent merges STT-MRAM and eDRAM bit-cells into a hybrid structure where the MTJ device and capacitor share common transistors and interconnect lines. This integration allows the system to leverage the non-volatility of MRAM while using the capacitor to retain data during low-activity periods, reducing the need for frequent high-power refresh operations typical of pure eDRAM systems.
Solution Approach 2:
The hybrid bit-cell design enables the memory system to operate in multiple modes (volatile and non-volatile) using the same physical structure. The MTJ device can function as both a magnetic memory element and a resistive element, while the capacitor serves both as a charge storage element and a means to maintain data state, providing multi-functionality that reduces overall system complexity and power consumption.
2Speed
If eDRAM is used for embedded memory, then fast access is achieved, but low retention time due to leakage occurs
Solution Approach 1:
The patent combines eDRAM and MRAM functionalities in a single hybrid bit-cell, where the capacitor provides fast access characteristics during active periods while the MTJ device provides non-volatile storage. The shared transistor structure enables rapid switching between read and write operations, maintaining the speed advantages of eDRAM while extending retention through the magnetic memory element.
3Quantity of substance
If two separate bit-cells are integrated in a hybrid structure, then high-density packaging is achieved, but device complexity increases
Solution Approach 1:
The hybrid bit-cell merges two functional units (MRAM and eDRAM) into a single integrated structure that shares transistors, interconnect lines, and control logic. This consolidation achieves high memory density by effectively packing two bit-cells worth of functionality into the area of one conventional bit-cell, while the shared components reduce the overall complexity compared to implementing separate MRAM and eDRAM blocks.
Solution Approach 2:
The control logic and transistors in the hybrid bit-cell serve multiple functions: they control both the capacitor charge operations and the MTJ write/read operations. This multi-functionality reduces the number of dedicated control circuits needed, thereby lowering device complexity despite the enhanced functionality provided by the integrated MRAM-eDRAM structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hybrid bit-cell achieves fast accessibility and high performance under normal conditions while providing long retention time during low activity periods, enhancing energy and computational efficiency.
Implementation Method 1
a resistive memory element (e.g., Magnetic Tunnel Junction (MTJ) device)
Implementation Method 2
uses a Metal-Insulator-Metal (MIM) based capacitor
Data Source
AI summary
Described is an apparatus for a hybrid eDRAM and MRAM memory cell comprising: a capacitor having a first terminal and a second terminal; a first transistor having a gate terminal coupled to a first word line (WL), a source/drain terminal coupled to bit line (BL), and drain/source terminal coupled to the first terminal of the capacitor; a resistive memory element having a first terminal and a second terminal, the first terminal of the resistive memory element device coupled to the first terminal of the capacitor; and a second transistor having a gate terminal coupled to a second WL, a source/drain terminal coupled to source line (SL), and drain/source terminal coupled to the second terminal of the resistive memory element device.