Hybrid Equalizer Stages for Wide Data-Rate Signal Compensation
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Solution Overview
Problem
Existing equalizer circuitries face limitations in achieving a wide range of data rates due to capacitive loading constraints in non-inductor based designs and inability to reduce bandwidth in inductor based designs, leading to intersymbol interference and increased bit error rates.
Innovation Solution
The proposed equalizer circuitry combines both inductor based and non-inductor based stages, allowing for AC gain at lower frequencies with inductor stages powered on and higher frequencies with non-inductor stages powered off, thereby supporting a broader range of data rate applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If non-inductor based equalizer circuitry is used, then the circuitry can be used in lower data rate applications, but the capacitive loading on the output node limits the bandwidth and prevents achieving higher bandwidths
Solution Approach 1:
The patent combines both non-inductor based equalizer stages and inductor based equalizer stages in a hybrid architecture. The non-inductor stages handle lower frequency compensation while inductor stages extend the bandwidth to higher frequencies, thereby merging the advantages of both approaches to achieve wide bandwidth coverage for multiple data rates.
Solution Approach 2:
The hybrid equalizer circuitry is designed to serve multiple functions across different data rate applications. By incorporating both types of stages, the circuitry can adaptively compensate for frequency-dependent losses in both lower data rate applications (up to 14 Gbps) and higher data rate applications (greater than 20 Gbps), making it universally applicable across a wide range of speeds.
2Speed
If inductor based equalizer circuitry is used, then the AC gain peaks at higher bandwidth for data rates greater than 20 Gbps, but the bandwidth cannot be reduced to support lower data rates and the footprint in layout is larger
Solution Approach 1:
The equalizer circuitry is segmented into multiple stages with different functions. Non-inductor based stages are used for lower frequency compensation in lower data rate applications, while inductor based stages are used for higher frequency compensation in higher data rate applications. This segmentation allows each stage to be optimized for its specific frequency range, enabling the overall system to support a wide range of data rates.
Solution Approach 2:
The hybrid equalizer architecture enables dynamic adaptation to different data rate requirements. By selectively activating appropriate stages based on the operating data rate, the circuitry can dynamically adjust its bandwidth characteristics to match the application requirements, whether for lower data rates (using non-inductor stages) or higher data rates (using inductor stages).
3Reliability
If equalizer circuitry is used to compensate for frequency dependent losses, then intersymbol interference is reduced, but the circuitry complexity increases
Solution Approach 1:
Different parts of the equalizer circuitry have different local qualities optimized for specific frequency ranges. Non-inductor based stages provide compensation for lower frequency losses with simpler circuitry, while inductor based stages provide compensation for higher frequency losses with more complex circuitry. This local quality differentiation allows the system to achieve reliable compensation across the entire frequency spectrum while minimizing overall complexity by using simpler stages where possible.
Data Source
AI summary
An equalizer circuitry that includes both inductor based and non-inductor based equalizer stages is provided. In one implementation, the equalizer circuitry includes a first equalizer circuitry including a first inductor based equalizer stage and a first non-inductor based equalizer stage coupled to the first inductor based equalizer stage. In one implementation, the equalizer circuitry further includes a second equalizer circuitry including a plurality of inductor based equalizer stages, where the plurality of inductor based equalizer stages includes the first inductor based equalizer stage. In one implementation, the first equalizer circuitry further includes a second inductor based equalizer stage coupled to the first inductor based equalizer stage and the first non-inductor based equalize stage.