Hybrid-Equivalence Partition Computing for Power Electronics
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Solution Overview
Problem
Conventional whole circuit simulation methods for large-scale power electronics systems face challenges due to high model dimension and low computing efficiency, exacerbated by the increasing scale of power electronics systems and limited processor computing power.
Innovation Solution
A hybrid-equivalence-based power electronics system partition computing method that involves collecting statistics on series loops and parallel nodes, establishing node voltage equations, performing classification conversions, and implementing hybrid equivalent conversions to enable efficient decoupling and parallel computing of sub-partitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional whole circuit simulation method is adopted, then simulation accuracy is maintained, but computing efficiency deteriorates due to large model dimension
Solution Approach 1:
The patent divides the entire power electronics circuit into multiple independent sub-circuits based on topological analysis. Each sub-circuit is simulated separately using equivalent models, reducing the overall model dimension. This segmentation allows parallel computation while maintaining simulation accuracy through proper coupling of sub-circuits via equivalent circuits.
Solution Approach 2:
The patent introduces equivalent circuits as intermediary elements to represent the coupling relationships between sub-circuits. These equivalent circuits act as mediators that preserve the electrical characteristics and interactions of the original circuit while enabling independent simulation of each sub-circuit, thus maintaining accuracy while improving efficiency.
2Adaptability or versatility
If the power electronics system scale increases, then system capability is improved, but processor computing power becomes insufficient
Solution Approach 1:
The patent segments large-scale power electronics systems into modular sub-circuits that can be independently simulated. This segmentation reduces the computational burden on processors by breaking down the large system into manageable parts, allowing the system to scale without proportionally increasing processor requirements.
Solution Approach 2:
The patent transforms the simulation problem from a single large-scale computation into multiple smaller computations that can be executed in parallel across different processors or cores. This dimensional change from sequential to parallel computation allows the system to handle larger scales by utilizing additional computational resources rather than overloading a single processor.
3Productivity
If circuit partitioning based on Thevenin equivalent method is used, then computing efficiency is improved, but decoupling computing efficiency deteriorates in complex series and parallel systems
Solution Approach 1:
The patent applies different equivalent circuit models (Thevenin, Norton, or other appropriate models) to different sub-circuits based on their specific characteristics and coupling types. This local quality approach optimizes the equivalent representation for each sub-circuit individually, improving decoupling efficiency in complex series and parallel configurations where a single universal model would be insufficient.
Data Source
AI summary
The present invention discloses a hybrid-equivalence-based power electronics system partition computing method, and relates to the field of power electronics simulation. In the power electronics system partition computing method, by separating series nodes and parallel nodes from internal nodes, converting the series nodes into an impedance form, and converting the parallel nodes into an admittance form, hybrid equivalent conversion of sub-partitions is implemented. By projecting hybrid equivalent matrices and hybrid excitation matrices of the sub-partitions onto a global coupling coordinate system, there is linear additivity between the hybrid equivalent matrices of the sub-partitions, and a series coupling current and a parallel coupling voltage of a system are efficiently solved, thereby implementing parallel partition decoupling computing of the power electronics system.