Hybrid Erase Sequencing for 3D NAND Data Retention
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Solution Overview
Problem
Existing erase operations in semiconductor memory devices, particularly in 3D NAND structures, suffer from data retention issues due to inter-word line hole accumulation during the erase process, which is exacerbated by concurrent erasing of memory cells connected to all word lines, leading to lateral movement of electrons in the charge trapping layers.
Innovation Solution
Implementing an erase operation that includes an all word line erase phase followed by an odd-even word line erase phase, where the transition to the odd-even phase is triggered based on a first verify test indicating reduced threshold voltages, optimizing the erase voltage levels to minimize time and inter-word line hole accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If concurrent erase operation is performed on all memory cells connected to all word lines, then erase time is reduced and productivity is improved, but inter-word line hole accumulation increases causing data retention degradation
Solution Approach 1:
The erase operation is segmented into two distinct phases: an all-word-line erase phase that erases all memory cells simultaneously for speed, followed by an odd-even word-line erase phase that selectively erases only odd or even word lines to remove accumulated holes. This segmentation allows the system to achieve both fast initial erasure and subsequent data retention improvement.
Solution Approach 2:
The patent implements periodic alternating erase operations where odd-word-line erase and even-word-line erase are performed in alternating cycles. This periodic action gradually removes accumulated holes from inter-word-line regions while maintaining overall erase efficiency, addressing the data retention issue without completely sacrificing productivity.
2Productivity
If erase voltage is increased to improve erase speed, then productivity increases, but inter-word line hole accumulation is exacerbated worsening data retention
Solution Approach 1:
The high-voltage erase operation is segmented into two phases: initial high-voltage all-word-line erase for speed, followed by lower-voltage odd-even alternating erase to remove accumulated holes. This segmentation allows aggressive erasure initially while gentler subsequent operations clean up the harmful hole accumulation.
Solution Approach 2:
The all-word-line erase phase is performed as a preliminary action to quickly establish the erased state across all memory cells. This preliminary high-speed erase is followed by the odd-even alternating phase that addresses the side effect (hole accumulation) created by the initial operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data retention by reducing inter-word line hole accumulation while balancing erase time, thereby improving the overall performance and longevity of memory cells.
Implementation Method 1
A charge-trapping material can be arranged vertically in a three-dimensional (3D) stacked memory structure, or horizontally in a two-dimensional (2D) memory structure
Implementation Method 2
The memory structure 126 includes a tunneling layer 665 between the charge trapping layer 664 and the channel 660
Data Source
Figure 1A~1B
Figure 1C
Figure 2
AI summary
Apparatuses and techniques are described for performing an erase operation for a set of memory cells, where the erase operation includes an all word line erase phase to save time followed by an odd-even word line erase phase to improve data retention. A transition to the odd-even word line erase phase can be triggered when the memory cells pass a first verify test which indicates that the threshold voltages of the memory cells have decreased below a first voltage. Or, the transition can be triggered when a threshold number of erase-verify iterations have been performed. The erase operation may be completed when the memory cells pass a second verify test which indicates that the threshold voltages of the memory cells have decreased below a second voltage which is less than the first voltage.