Hybrid eSCM DIMM Data Placement for Low Latency Storage

The storage class memory is segmented into multiple memory types (DRAM, SRAM, and non-volatile memory) organized in a hierarchical structure. Each segment serves different purposes: DRAM for frequently accessed data requiring low latency, SRAM for cache operations, and non-volatile memory for persistent storage. This segmentation allows the system to achieve non-volatility while maintaining low latency for active data through intelligent data placement and management.

The system employs periodic data migration between memory types based on access patterns and power states. During active periods, frequently accessed data is migrated to DRAM for low-latency access. During idle or low-power periods, data is migrated back to non-volatile memory to reduce overall power consumption. This periodic action allows the system to dynamically balance between performance and power efficiency while maintaining non-volatility.

The system merges multiple memory technologies (DRAM, SRAM, and non-volatile memory) into a unified storage class memory architecture. This combination allows the system to leverage the high speed of DRAM/SRAM for active data while utilizing the high capacity and low cost of non-volatile memory for persistent storage. The merged architecture presents a unified interface to the processor, hiding the complexity of data distribution across different memory types and providing both high performance and large capacity.

The system applies local quality by assigning different memory types to different data based on access patterns and importance. Critical and frequently accessed data resides in expensive but fast DRAM/SRAM, while less frequently accessed data is stored in cheaper non-volatile memory. This localized allocation of memory resources optimizes the overall cost-effectiveness of the storage class memory system while maintaining non-volatility for all data through the presence of non-volatile memory in the hierarchy.