Hybrid FD-SOI and RF-SOI Structure for Loss and Back-Bias Tradeoffs
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Solution Overview
Problem
Existing semiconductor-on-insulator structures, particularly double-BOX FD-SOI structures, are incompatible with both digital and radiofrequency applications due to electrical losses in the substrate and limited maximum power rating, which hinders the development of high-quality PN junctions and radiofrequency components.
Innovation Solution
A semiconductor-on-insulator structure with a high-resistivity carrier substrate, multiple insulating layers, and a charge-trapping layer, combined with FD-SOI and RF-SOI regions, allowing for the integration of digital and radiofrequency components by optimizing the thickness and material properties of the insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-resistivity substrate is used to compensate for electrical losses and improve RF performance, then RF performance is improved, but the substrate becomes incompatible with transistors whose threshold voltage is controlled via back-side gate
Solution Approach 1:
The structure is divided into distinct functional regions: an RF-SOI region with high-resistivity substrate and thick BOX for RF components, and an FD-SOI region with standard substrate and thin BOX for digital transistors requiring back bias control. This segmentation allows each region to be optimized for its specific application without compromising the other.
Solution Approach 2:
Different substrate and BOX layer configurations are applied locally to different regions of the semiconductor structure. The RF-SOI region uses high-resistivity substrate with thick BOX to minimize electrical losses, while the FD-SOI region uses standard substrate with thin BOX to enable back bias control, giving each local area the quality it needs for its function.
2Reliability
If double-BOX structures are used for digital applications, then digital performance is improved, but the structure is incompatible with radiofrequency applications due to limited maximum power rating
Solution Approach 1:
The semiconductor structure is segmented into separate RF-SOI and FD-SOI regions, each with optimized BOX layer configurations. The FD-SOI region maintains the double-BOX structure for digital performance, while the RF-SOI region uses a thick BOX structure to achieve high breakdown voltage for RF power applications.
Solution Approach 2:
Different BOX layer thicknesses are applied locally: thin BOX layers in the FD-SOI region for digital transistor control, and a thick BOX layer in the RF-SOI region to withstand high voltages and power levels required for RF amplifiers and switches.
3Reliability
If a charge-trapping layer is added to improve RF performance, then electrical losses are compensated, but the layer hinders back biasing and accelerates dopant diffusion
Solution Approach 1:
The charge-trapping layer is selectively placed only in the RF-SOI region where it is needed for compensating electrical losses, while being absent from the FD-SOI region where high-quality PN junctions requiring precise doping are fabricated. This spatial segmentation allows the charge-trapping functionality to be activated only where beneficial.
Solution Approach 2:
The charge-trapping layer is applied locally to the RF-SOI region to provide electrical loss compensation specifically where RF components are located, while leaving the FD-SOI region without this layer to maintain the quality and precision of PN junctions and dopant profiles required for digital devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure enhances both digital and radiofrequency performance by reducing electrical losses and increasing the breakdown voltage, enabling the production of high-quality transistors and radiofrequency components.
Implementation Method 1
forming a weakened zone in the first donor substrate, so as to delineate an intermediate first semiconductor layer; transferring the intermediate first semiconductor layer to a semiconductor carrier substrate
Data Source
AI summary
The present disclosure relates to a multilayer semiconductor-on-insulator structure, comprising, successively from a rear face toward a front face of the structure: a semiconductor carrier substrate with high electrical resistivity, whose electrical resistivity is between 500 Ω·cm and 30 kΩ·cm, a first electrically insulating layer, an intermediate layer, a second electrically insulating layer, which has a thickness less than that of the first electrically insulating layer, an active semiconductor layer, the multilayer structure comprises: at least one FD-SOI region, in which the intermediate layer is an intermediate first semiconductor layer, at least one RF-SOI region, adjacent to the FD-SOI region, in which the intermediate layer is a third electrically insulating layer, the RF-SOI region comprising at least one radiofrequency component plumb with the third electrically insulating layer.