Hybrid FFT DSP Engine With Feedback Loop for Low-Latency Processing
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Solution Overview
Problem
Existing integrated circuit devices struggle to efficiently perform both digital signal processing and machine learning tasks due to circuitry that is not well suited for both applications, particularly in high-throughput communication technologies like 5G, leading to increased latency and power consumption.
Innovation Solution
A digital signal processing (DSP) block with a combination of fixed and variable Fast Fourier Transform (FFT) engines and a scale/offset block, integrated with a feedback loop, to perform multiple FFT operations without data read/write from the hardware accelerator, reducing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate circuitry is used for digital signal processing and machine learning, then each application can be optimized independently, but device complexity and area increase
Solution Approach 1:
The DSP block is designed to perform multiple functions including FFT operations, digital signal processing, and machine learning tasks through a single integrated circuit. The circuit includes configurable elements such as programmable logic devices that can be programmed to execute different algorithms, and a unified architecture that supports both convolutional neural networks and traditional DSP operations, eliminating the need for separate dedicated circuitry for each application type.
2Measurement precision
If data is read from and written to hardware accelerator for each FFT operation, then data accuracy is maintained, but latency increases
Solution Approach 1:
Input data is pre-loaded into on-chip buffer memory before processing begins. The architecture allows data to be staged in local memory buffers during idle periods or in parallel with processing operations, so that when FFT computations are initiated, the data is already available in high-speed memory rather than requiring external reads during critical processing intervals.
Solution Approach 2:
The system implements a hierarchical memory structure with multiple levels of buffering. Local on-chip buffers are nested within the DSP block, which itself is nested within the broader system memory architecture. This nested arrangement allows data to be cached at multiple levels, with the innermost buffers providing fastest access for critical FFT operations while maintaining data integrity through controlled data flow paths.
3Quantity of substance
If external memory access is used for FFT operations, then data capacity is sufficient, but power consumption increases
Solution Approach 1:
The memory system is segmented into multiple distinct buffers located at different hierarchical levels. Small, frequently accessed datasets are stored in small, low-power on-chip buffers that consume minimal power. Larger datasets that are accessed less frequently can be stored in external memory, with data being transferred in batches rather than continuously. This segmentation allows the system to optimize power consumption by keeping only essential data in power-hungry external memory while maintaining adequate capacity through the combined hierarchical structure.
Data Source
AI summary
A digital signal processing (DSP) block includes a Fast Fourier Transform (FFT) unit capable of performing an FFT operation. The FFT unit includes a first FFT engine capable of converting a signal between a time-domain and a frequency-domain and the first FFT engine is a fixed size FFT engine. The FFT unit also includes a second FFT engine communicatively coupled to the first FFT engine and the second FFT engine is a variable size FFT engine. The FFT unit also includes a scale/offset block communicatively coupled to the second FFT engine and the scale/offset block is capable of performing a multiplication operation, an addition operation, or a combination thereof on an output of the second FFT engine.