FFT Processor Combining Cooley-Tukey and Pease for SIMD Speed
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Solution Overview
Problem
Existing FFT computation methods in vector processors face challenges with low execution speed, high hardware overhead, and limited hardware reusability due to complex shuffling operations and dedicated hardware requirements, particularly in long FFT computations.
Innovation Solution
A hybrid FFT computation method using a combination of Cooley-Tukey and Pease FFT algorithms, where long FFTs are decomposed into smaller parts processed using Cooley-Tukey for initial stages and Pease FFT for subsequent stages, with a simplified shuffling mechanism that decouples butterfly and shuffling operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dedicated hardware and complex shuffling operations are used for FFT computation, then computation accuracy is improved, but device complexity and hardware overhead increase
Solution Approach 1:
The patent applies universality by making existing SIMD/vector processor resources perform multiple functions. The computation resources originally designed for general-purpose SIMD operations are made to also perform FFT-specific butterfly operations and shuffling operations through software configuration, eliminating the need for dedicated FFT hardware while maintaining computational accuracy.
Solution Approach 2:
The patent substitutes mechanical/dedicated hardware systems with software-based implementations. Instead of using dedicated FFT hardware circuits for butterfly operations and data shuffling, the invention uses programmable SIMD/vector processor instructions to perform these operations, reducing hardware complexity while maintaining functionality.
2Measurement precision
If complex shuffling operations are performed in each FFT stage, then computation accuracy is improved, but execution speed decreases
Solution Approach 1:
The patent extracts the shuffling operations from the critical computation path. By separating the butterfly computation from the data shuffling operations and performing shuffling outside the main computation loop or using optimized memory access patterns, the invention maintains computational accuracy while reducing the execution time impact of shuffling operations.
3Measurement precision
If dedicated hardware resources are allocated for FFT computation, then computation accuracy is improved, but hardware reusability decreases
Solution Approach 1:
The patent makes existing SIMD/vector processor resources perform multiple functions. The computation resources originally designed for general-purpose SIMD operations are made to also perform FFT-specific butterfly operations and shuffling operations through software configuration, eliminating the need for dedicated FFT hardware while maintaining computational accuracy.
4Productivity
If vectorization is applied to N-point DFT, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by utilizing the existing SIMD/vector processor architecture and its inherent parallel processing capabilities to perform FFT operations. The processor's own vector registers and parallel execution units are leveraged to accelerate FFT computation without requiring additional dedicated hardware, thus improving productivity while avoiding increased hardware complexity.
Data Source
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AI summary
Described is a processor (1602) for processing a signal using a fast Fourier transform, the processor (1602) being configured to: receive (1401) a signal comprising input data of N samples; and perform a Fourier transform operation on the input data of N samples by: taking the input data of N samples as initial input, forming (1402) an intermediate result by performing one or more Fourier transform stages using one or more Fourier transform operations of a first type; and taking the intermediate result as input, forming (1403) an output by performing one or more Fourier transform stages on the intermediate result using one or more Fourier transform operations of a second type. This may improve execution speed, data memory size and hardware scalability of FFT/iFFT computation using SIMD/vector processors.