Hybrid FIFO RAM Buffer Circuit for Clock Domain Crossing
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Solution Overview
Problem
Existing clock domain crossing buffers face challenges in balancing capacity, latency, and physical size, leading to data integrity issues and performance degradation in high-speed communication applications, particularly in real-time data transmissions.
Innovation Solution
A buffer circuit that combines a flip-flop based FIFO with a RAM FIFO, using selection logic to divert data to the RAM FIFO when the flip-flop FIFO reaches capacity, allowing for efficient reloading and maintaining low latency while minimizing physical size and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a discrete buffering device is used to accommodate data rate differences between clock domains, then data integrity is maintained, but data transit latency increases
Solution Approach 1:
The buffer is segmented into two distinct parts: a first-in first-out (FIFO) buffer for low-latency data transfer and a random access memory (RAM) buffer for high-capacity storage. The selection logic dynamically routes data between these two segments based on the operational state, allowing the system to achieve both data integrity and low latency by utilizing the appropriate segment for each data transfer operation.
Solution Approach 2:
The buffer system dynamically switches between FIFO and RAM modes based on real-time conditions. The selection logic monitors the buffer state and dynamically routes data through the optimal path: using FIFO for low-latency transfers when data rates are matched, and switching to RAM for high-capacity buffering when data rate differences exist between clock domains. This dynamic adaptation resolves the contradiction by adjusting the buffering mechanism to match operational requirements.
2Quantity of substance
If a large capacity FIFO buffer is used to store data between clock domains, then data capacity increases, but physical size and cost increase
Solution Approach 1:
The invention merges two different buffering technologies (FIFO and RAM) into a single hybrid buffer system. The FIFO portion handles low-latency data transfer with small physical footprint, while the RAM portion provides high-capacity storage. By combining these two approaches, the system achieves large effective data capacity without requiring a proportionally large physical buffer, as the RAM is only activated when high-capacity buffering is actually needed.
Solution Approach 2:
The buffer system uses selection logic that automatically determines when to use the FIFO portion versus the RAM portion based on the operational state. This self-service mechanism eliminates the need for external control circuitry to manage the entire buffer, allowing the system to efficiently utilize the smaller FIFO structure for routine operations and only engage the larger RAM structure when necessary, thereby optimizing the physical size-to-capacity ratio.
3Quantity of substance
If a RAM-based FIFO is used to increase buffer capacity, then data capacity increases, but read data latency is introduced
Solution Approach 1:
The buffer is segmented into two distinct parts: a first-in first-out (FIFO) buffer for low-latency data transfer and a random access memory (RAM) buffer for high-capacity storage. The selection logic dynamically routes data between these two segments based on the operational state, allowing the system to achieve both data integrity and low latency by utilizing the appropriate segment for each data transfer operation.
Solution Approach 2:
The system changes the operational parameter of the buffer by switching between FIFO mode and RAM mode. When low latency is required, the system operates in FIFO mode with direct data transfer. When high capacity is required, the system switches to RAM mode. This parameter change allows the system to optimize between capacity and latency based on real-time requirements, resolving the contradiction by making the buffer characteristics adaptable rather than fixed.
Data Source
AI summary
Systems, devices, and methods, including logic and/or executable instructions are described in connection with a buffer circuit. One buffer circuit includes a flip-flop based first-in first-out (FIFO) buffer having an input and an output, selection logic coupled in series with the FIFO buffer input, and a random access memory (RAM) FIFO coupled in parallel with the selection logic. The selection logic diverts incoming data to the RAM FIFO after the FIFO buffer is filled to a first capacity level, and reloads the FIFO buffer using data from the RAM FIFO until the RAM FIFO is emptied to a second capacity level. Data is extracted without read data latency from the output of the FIFO buffer as an output of the buffer circuit.