Hybrid Fin Gate Structure Without Cladding Footing Leakage
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Solution Overview
Problem
Nanostructure transistors face fabrication challenges that lead to performance issues and device failures due to cladding sidewall layer protrusions and footings, causing electrical shorting and reduced yield, especially as gate length decreases and technology nodes shrink.
Innovation Solution
The cladding sidewall layer footing is removed prior to forming a hybrid fin structure, and the cladding sidewall layers are formed asymmetrically to prevent metal gate footings, allowing for the formation of metal gates around nanostructure channels without electrical shorting, thereby reducing short channel effects and leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cladding sidewall layers are formed to enable metal gate formation around nanostructure channels, then gate-all-around control is achieved, but protrusions and footings cause electrical shorting and device failure
Solution Approach 1:
The patent performs preliminary removal of cladding sidewall layer footings from shallow trench isolation regions before forming the metal gate structure. This preliminary action prevents the footings from causing electrical shorting between the metal gate and source/drain contacts, thereby resolving the harmful effect while maintaining the gate-all-around configuration
Solution Approach 2:
The patent extracts and removes the problematic cladding sidewall layer footings from the shallow trench isolation regions. By taking out these harmful protrusions before metal gate formation, the patent eliminates the source of electrical shorting while preserving the functional cladding sidewall layers that enable gate-all-around control
2Productivity
If gate length is reduced for smaller technology nodes, then transistor density increases, but source/drain electron tunneling increases causing higher off current
Solution Approach 1:
The patent forms asymmetric cladding sidewall layers with different lengths on opposite sides of the nanostructure channels. The longer cladding sidewall layers extend further into the shallow trench isolation regions, creating asymmetric barriers that effectively suppress source/drain electron tunneling and reduce off-current, while allowing the metal gate to maintain gate-all-around control
Solution Approach 2:
The patent applies different cladding sidewall layer lengths at different locations around the nanostructure channels. The asymmetric lengths provide localized enhancement of barrier properties where electron tunneling is most problematic, while maintaining appropriate gate control in other regions
Data Source
AI summary
A cladding sidewall layer footing is removed prior to formation of a hybrid fin structure. Removal of the cladding sidewall layer footing prevents a metal gate footing from forming under the hybrid fin structure when the cladding sidewall layer is removed to enable the metal gate to be formed around the nanostructure channels of a nanostructure transistor. Cladding sidewall layers can be formed in an asymmetric manner to include different lengths and/or angles, among other examples. The asymmetric cladding sidewall layers enable asymmetric metal gate structures to be formed for p-type and n-type nanostructure transistors while preventing metal gate footings from forming under hybrid fin structures for p-type and n-type nanostructure transistors. This may reduce a likelihood of short channel effects and leakage within the nanostructure transistors yield of nanostructure transistors formed on a semiconductor substrate.