Hybrid Fin Gate Stack Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The scaling down of Integrated Circuit (IC) technology has increased complexity in processing and manufacturing, particularly with multi-gate devices, where high-K dielectric layers can cause parasitic coupling between the metal gate and adjacent source/drain contact plugs, degrading device performance.
Innovation Solution
A hybrid fin structure with a high-K dielectric layer is used, which is uncovered by the gate stack through anisotropic and isotropic etching, reducing parasitic capacitance by forming a high-K dielectric layer directly under the gate stacks and preventing lateral merging of source/drain features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-K dielectric layer is used in multi-gate devices, then device performance is improved through better gate control, but parasitic coupling between the metal gate and adjacent source/drain contact plugs increases, degrading device performance
Solution Approach 1:
The patent removes the high-K dielectric layer from regions adjacent to source/drain contact plugs while maintaining it under the gate. This selective extraction eliminates the parasitic coupling path between metal gate and contact plugs, resolving the contradiction by preserving the beneficial gate control where needed while removing the harmful parasitic effects where they occur.
Solution Approach 2:
The patent implements spatially varying dielectric properties by maintaining the high-K dielectric layer only in specific regions (under the gate) while removing it from other regions (adjacent to contact plugs). This local differentiation allows the structure to simultaneously achieve strong gate control where the high-K layer is present and low parasitic capacitance where it is removed.
2Productivity
If geometry sizes are scaled down to increase functional density, then production efficiency is improved and costs are lowered, but processing and manufacturing complexity increases
Solution Approach 1:
The patent divides the high-K dielectric layer into discrete regions - present under the gate and absent near contact plugs. This segmentation allows selective optimization of different areas for different functions, enabling scaled-down geometries to be manufactured with controlled complexity by addressing specific regional requirements rather than treating the entire structure uniformly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by reducing parasitic capacitance and maintaining the effectiveness of the high-K dielectric layer, thereby improving the functionality of multi-gate transistors.
Implementation Method 1
uncovered by the gate stack through anisotropic and isotropic etching
Implementation Method 2
uncovered by the gate stack through anisotropic and isotropic etching
Implementation Method 3
high-K dielectric layers can cause parasitic coupling between the metal gate and adjacent source/drain contact plugs
Data Source
AI summary
Provided are a semiconductor device and a method of forming the same. The semiconductor device includes at least two active strip regions, a hybrid fin structure, and a gate stack. The hybrid fin structure is disposed between the at least two active strip regions. The gate stack is across the at least two active strip regions and the hybrid fin structure. A portion of the hybrid fin structure exposed by the gate stack is free of a high dielectric constant material.