Hybrid Fin Gate Width Tuning for DIBL Matching
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Solution Overview
Problem
Hybrid fin devices face challenges in optimizing performance, density, efficiency, and fabrication costs due to differences in electrical characteristics between single-fin and multi-fin transistors, exacerbated by shrinking IC technology nodes, which affect drain-induced barrier lowering (DIBL) and other short channel effects.
Innovation Solution
The solution involves adjusting the width of the gate in hybrid fin devices using optical proximity correction (OPC) rules to minimize differences in electrical characteristics between single-fin and multi-fin transistors, ensuring that both types of transistors have substantially the same DIBL, thereby improving overall performance and integrating seamlessly into existing IC manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate width is increased to improve electrical performance of single-fin devices, then DIBL is reduced, but device density and area utilization deteriorate
Solution Approach 1:
The patent applies different gate widths to different fin structures within the same gate line. Specifically, gates overlying single-fin structures have a first width, while gates overlying multi-fin structures have a second width. This local differentiation allows each fin type to be optimized for its electrical characteristics without compromising overall device density.
Solution Approach 2:
The gate line is segmented into multiple portions, each tailored to the specific fin structure it overlays. The method divides the gate structure into discrete segments with different widths corresponding to single-fin and multi-fin regions, enabling independent optimization of electrical performance for each segment while maintaining high area utilization.
2Productivity
If device dimensions are scaled down to increase functional density, then production efficiency improves, but differences in electrical characteristics between single-fin and multi-fin devices are exacerbated
Solution Approach 1:
The patent implements local quality adjustment by assigning different gate widths to single-fin and multi-fin structures. This allows compensation for the exacerbated electrical characteristic differences that occur during scaling, as each fin type receives a customized gate width optimized for its specific electrical behavior at reduced dimensions.
Solution Approach 2:
The method changes the gate width parameter based on the fin structure type. By adjusting this critical dimension parameter locally, the patent compensates for scaling-induced variations in electrical characteristics, maintaining uniformity in device performance despite reduced overall device dimensions.
3Ease of manufacture
If uniform gate width is used across all fin structures to simplify manufacturing, then fabrication complexity is reduced, but electrical performance optimization is compromised
Solution Approach 1:
The patent incorporates gate width adjustments during the mask preparation stage, specifically through optical proximity correction (OPC). This preliminary action embeds the differentiated gate widths into the manufacturing process itself, allowing complex electrical optimization without adding significant fabrication complexity, as the variations are built into the master mask rather than requiring additional manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces electrical characteristic differences between single-fin and multi-fin devices, enhancing the performance and efficiency of hybrid fin devices while maintaining minimal changes to existing manufacturing processes, thereby improving the hybrid fin device's performance and reducing fabrication costs.
Implementation Method 1
differences in electrical characteristics, such as drain-induced barrier lowering (DIBL), between single-fin and multi-fin transistors
Data Source
AI summary
An exemplary method includes receiving a hybrid fin device layout for a hybrid fin device that includes a gate disposed over a single-fin active region and a multi-fin active region. The single-fin active region and the multi-fin active region extend lengthwise along a first direction. The gate extends lengthwise along a second direction, the second direction is different than the first direction, and the gate has a width along the first direction. The single-fin active region and a first portion of the gate form a first fin-based device having a first electrical characteristic. The multi-fin active region and a second portion of the gate form a second fin-based device having a second electrical characteristic that is different than the first electrical characteristic. The method further includes tuning the width of the gate to reduce a difference between the first electrical characteristic and the second electrical characteristic.