Hybrid FinFET SRAM Cell Layout for Density and Stability
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, issues such as cross-talk and wiring resistance affect their performance, particularly in static random access memory (SRAM) devices, where existing technologies struggle to maintain high-density integration and stability without compromising read and write margins.
Innovation Solution
The implementation of a hybrid memory cell architecture that combines single-fin and multiple-fin FinFET transistors within a single SRAM memory chip, eliminating the need for read assist circuitry in all memory cells, and utilizing a co-optimized layout of hybrid single-fin and multiple-fin cells to achieve high-density integration and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cell density is increased to improve integration, then productivity is improved, but cross-talk and wiring resistance increase causing performance degradation
Solution Approach 1:
The patent divides the memory chip into two distinct memory regions: a first memory region with first memory cells and a second memory region with second memory cells. This segmentation allows different cell designs to be used in different regions, optimizing for both high density and high performance without requiring read assist circuitry in all cells.
Solution Approach 2:
The patent applies different memory cell structures to different regions of the memory chip. The first memory cells in the first region are designed for high density without read assist circuitry, while the second memory cells in the second region are designed for high performance with improved read margins. This local differentiation allows each region to have optimized characteristics for its specific function.
2Reliability
If read assist circuitry is added to all memory cells to improve read performance, then reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements read assist circuitry only in the second memory region where high read performance is critical, while the first memory region operates without read assist circuitry. This selective application reduces overall device complexity and manufacturing cost while maintaining high read performance where needed.
Solution Approach 2:
The patent segments the memory array into regions with and without read assist circuitry, allowing the system to achieve high overall performance without requiring every single memory cell to have complex assist circuitry. The second memory region with read assist circuitry compensates for performance requirements while the first region provides high-density storage.
3Productivity
If memory cells are made smaller to increase density, then productivity is improved, but alpha ratios deteriorate and manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent divides the memory into two regions with different cell size optimizations. The first memory cells are optimized for minimal size to achieve high density, while the second memory cells are optimized for manufacturability and performance with larger dimensions that maintain better alpha ratios and are easier to manufacture with precision.
Solution Approach 2:
The patent uses different aspect ratios for the first and second memory cells. The first memory cells have aspect ratios optimized for high density packing, while the second memory cells have aspect ratios optimized for manufacturing precision and alpha ratio control. This parameter differentiation allows each region to achieve its specific optimization goals.
Data Source
AI summary
An integrated circuit includes a plurality of first memory cells and a plurality of second memory cells. Each cell of the plurality of first memory cells includes a first inverter, a second inverter, a first pass-gate (PG) transistor and a second PG transistor. Each inverter of the first and second inverters includes a P-type single FinFET transistor and an N-type single FinFET transistor. The first PG transistor and the second PG transistor each are an N-type single FinFET transistor. Each cell of the plurality of second memory cells includes a third inverter, a fourth inverter, a third PG transistor and a fourth PG transistor. Each inverter of the third and fourth inverters includes a P-type single FinFET transistor and an N-type transistor. Each transistor of the third and fourth PG transistors include at least two FinFET transistors electrically coupled in a parallel configuration.