Hybrid FinFET Strain Engineering for NMOS PMOS Performance
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Solution Overview
Problem
Current approaches to enhancing transistor performance by applying strain to semiconductor channel materials are incomplete, as they typically use the same type of strain for both NMOS and PMOS devices, limiting the effectiveness of advanced transistor geometries like PDSOI and FinFETs, especially when channel thickness is very small.
Innovation Solution
The use of different channel materials and strain levels for NMOS and PMOS devices, with Si-Ge alloys being preferred for NMOS and higher Ge content alloys under compressive strain for PMOS, along with varying substrate and process techniques to achieve optimal performance, including the use of group IV, III-V, and II-VI materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same type of strain is applied to both NMOS and PMOS devices, then process simplicity is maintained, but overall device performance is limited
Solution Approach 1:
The patent applies different strain types (tensile for NMOS, compressive for PMOS) to different device regions by using selective epitaxial growth with different semiconductor materials (e.g., SiGe for compressive strain in PMOS, Si for tensile strain in NMOS). This local differentiation of material properties enables optimized performance for each device type while maintaining a unified fabrication process flow.
2Reliability
If multilayer channel materials are used to achieve different strain types, then device performance is enhanced, but the total channel thickness becomes too great for fully depleted operation
Solution Approach 1:
The patent segments the channel into two distinct single-layer regions: one region uses a first semiconductor material (e.g., Si) for NMOS devices requiring tensile strain, and another region uses a second semiconductor material (e.g., SiGe) for PMOS devices requiring compressive strain. Each segment is independently optimized with appropriate thickness control to enable fully depleted operation while achieving the required strain characteristics for each device type.
3Ease of manufacture
If traditional single-material channel is used for both NMOS and PMOS, then manufacturing is simplified, but carrier mobility enhancement is incomplete
Solution Approach 1:
The patent changes the material composition parameter of the semiconductor channel by using different semiconductor materials with different lattice constants for NMOS and PMOS devices. Specifically, SiGe alloys with higher Ge content are used for PMOS to induce compressive strain, while Si or SiGe with lower Ge content is used for NMOS to induce tensile strain. This parameter variation enables significant carrier mobility enhancement in both device types while maintaining compatibility with standard CMOS fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved performance of NMOS and PMOS devices by customizing channel materials and strain levels, enabling fully depleted operation in advanced transistor geometries and enhancing carrier mobility, thereby overcoming the limitations of traditional methods.
Implementation Method 1
At least one of the first and second semiconductor materials may be tensilely strained and/or compressively strained
Data Source
AI summary
Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.