Hybrid FinFET Substrate Aligning 100 and 110 Crystal Orientations

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Solution Overview

Problem

The integration of both {110} and {111} crystallographic planes in a single FinFET or fin-type structure using high percentage SiGe or Ge materials is problematic due to lattice mismatch, affecting the performance of p-type and n-type MOSFETs in CMOS devices.

Innovation Solution

A hybrid substrate configuration is employed, with a top wafer of (100) silicon and a handle wafer of (110) silicon separated by a buried oxide layer, where fins oriented in the {100} direction on the top wafer and {110} direction on the handle wafer are aligned, allowing for the growth of HP SiGe or Ge fins with {110} and {111} crystallographic planes respectively, enabling the formation of both PFET and NFET structures on a single substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If HP SiGe or Ge is grown directly on silicon substrate, then high performance targets are achieved, but lattice mismatch causes defects

Engineering Contradiction:

Improvedevice performanceVSAvoidlattice mismatch defects

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The substrate is segmented into multiple layers with different crystal orientations: a (100) silicon substrate layer and a (110) silicon layer. This segmentation allows each layer to support specific fin orientations optimized for different transistor types, reducing lattice mismatch defects while maintaining high performance

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the substrate are assigned different crystal orientations tailored to specific device requirements. The (100) silicon substrate region supports fins optimized for one transistor type, while the (110) silicon layer supports fins optimized for the other transistor type, allowing each region to have the local quality needed for its specific function

Inventive Principle:

Principle #3Local quality

2Reliability

If both {110} and {111} crystallographic planes are used on a single FinFET structure, then both PFET and NFET performance are optimized, but integration becomes problematic

Engineering Contradiction:

Improvetransistor performanceVSAvoidsubstrate integration

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The solution moves from attempting to integrate different crystal orientations in the same physical plane to stacking them in vertical layers. The (100) silicon substrate and (110) silicon layer are arranged vertically, allowing each layer to support its optimal fin orientation without interfering with the other, thus reducing integration complexity

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

An intermediate (110) silicon layer is introduced between the (100) silicon substrate and the fins. This intermediate layer acts as a mediator that enables the formation of fins with different crystal orientations on the same substrate, facilitating the integration of both PFET and NFET optimized structures

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10177169B2Semiconductor device structure with 110-PFET and 111-NFET current flow direction

Publication Date: 2019.01.08 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A FinFET comprises a hybrid substrate having a top wafer of (100) silicon, a handle wafer of (110) silicon, and a buried oxide layer between the top wafer and the handle wafer; a first set of fins disposed in the top wafer and oriented in a <110> direction of the (100) silicon; and a second set of fins disposed in the handle wafer and oriented in a <112> direction of the (110) silicon. The first set of fins and the second set of fins are aligned.