Hybrid Flash Memory Device with Direct Module Data Transfer
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Solution Overview
Problem
As storage density increases in flash memory, read and program times, as well as data error rates, also increase, necessitating a novel design for a flash memory controller and access method that enhances speed and reduces errors.
Innovation Solution
A hybrid flash memory device comprising a single level memory module and a multi level memory module, where data is directly transmitted between the modules without passing through the controller, utilizing an anti-disturbance sub-page order to interlace programming operations and reduce voltage drift, while also employing error correction to recover data from adjacent memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If storage density is increased by using multi-level cell memory, then storage capacity is improved, but read and program time increases
Solution Approach 1:
The flash memory device is segmented into multiple memory modules with different cell types (SLC, MLC, TLC, QLC). Each module handles different data priorities and access patterns, allowing parallel processing and reducing overall access time while maintaining high storage density through the inclusion of multi-level cell modules.
Solution Approach 2:
A buffer memory module is introduced as an intermediary between the host and flash memory modules. The buffer temporarily stores data during write operations, enabling the controller to manage data transmission more efficiently and reduce the time penalty associated with high-density multi-level cell memory operations.
2Quantity of substance
If storage density is increased by using multi-level cell memory, then storage capacity is improved, but data error rate increases
Solution Approach 1:
Data is segmented and distributed across multiple memory modules with different error characteristics. SLC modules store critical or frequently accessed data with lower error rates, while MLC/TLC/QLC modules store less critical data. This segmentation allows the system to achieve high overall storage density while maintaining data reliability through diverse storage media.
Solution Approach 2:
The controller implements error detection and correction mechanisms that monitor data integrity across all memory modules. When errors are detected in high-density MLC/TLC/QLC modules, the system can retrieve redundant copies from SLC modules or initiate error correction procedures, providing feedback-based reliability assurance.
3Device complexity
If data is transmitted through the controller between memory modules, then data management is simplified, but transmission speed decreases
Solution Approach 1:
The buffer memory module serves as an intermediary that enables direct data transmission between flash memory modules without requiring constant controller intervention. The buffer absorbs data temporarily and facilitates direct module-to-module transfers, significantly improving transmission speed while the controller maintains simplified management through buffer coordination.
Solution Approach 2:
Data is preliminarily stored in the buffer memory module before being transferred to the final destination module. This preliminary action allows the system to prepare data in advance and execute high-speed direct transfers between modules, reducing the speed penalty that would otherwise result from controller-mediated transmission.
Data Source
AI summary
A flash memory device includes a flash memory and a controller. The flash memory includes a single level memory module and a multi level memory module. The single level memory module includes a first data bus and at least one single level cell flash memory. Each memory cell of the single level cell flash memory stores one bit of data. The multi level memory module includes a second data bus and at least one multi level cell flash memory. Each memory cell of the multi level cell flash memory stores more than one bit of data. The first data bus is coupled to the second data bus. During a write operation, the controller writes data to the single level memory module, and the single level memory module further transmits the data to the multi level memory module through the first and second data buses coupled therebetween without passing the data through the controller.