Hybrid Floating Gate Non-Volatile Memory Device
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In sub-20nm non-volatile memory devices, planar floating gate cells face issues with cell-to-cell interference and reduced control gate coupling ratio due to unwanted fringing capacitances, leading to program saturation and a decreased programming window, which existing high-k inter-gate dielectrics fail to adequately address.
Innovation Solution
A non-volatile memory device with a hybrid floating gate structure and a three-layer inter-gate dielectric structure, comprising high-k and low-k materials, where the first interfacial layer provides a potential energy drop below 0.5eV and is electrically transparent, optimizing the coupling ratio without affecting program saturation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-k inter-gate dielectric is used to increase the coupling ratio, then the programming window size increases, but charge leakage through the inter-gate dielectric increases causing program saturation
Solution Approach 1:
The inter-gate dielectric is segmented into multiple layers with alternating high-k and low-k materials. The high-k layers (e.g., HfO2, HfAlO) provide high capacitance for improved coupling ratio, while the low-k layers (e.g., SiO2, Al2O3) provide low leakage paths to prevent charge loss. This segmentation allows each layer to perform its specialized function, resolving the contradiction between high coupling ratio and low charge leakage.
Solution Approach 2:
The patent employs a composite inter-gate dielectric structure combining multiple dielectric materials with different properties. The high-k materials (HfO2 with k≈25, HfAlO with k≈20) are combined with low-k materials (SiO2 with k≈3.9, Al2O3 with k≈8). This composite structure achieves both high effective capacitance for coupling and low effective leakage by strategically positioning high-k and low-k layers throughout the stack.
2Reliability
If the inter-gate dielectric thickness is reduced to increase coupling ratio, then the programming window increases, but charge leakage increases causing program saturation
Solution Approach 1:
Instead of uniformly reducing thickness, the dielectric is segmented into multiple thin layers with alternating high-k and low-k materials. Each layer can be optimized independently - high-k layers provide capacitance with minimal thickness, while low-k layers provide leakage blocking. This segmentation enables achieving high coupling ratio without proportionally increasing leakage that would occur with simple thickness reduction.
Solution Approach 2:
The patent changes the dielectric parameters by introducing materials with different k-values and barrier heights at different positions in the stack. High-k materials with appropriate barrier heights are placed where capacitance is needed, while low-k materials with high barrier heights are placed where leakage prevention is critical. This parameter optimization allows thin overall structure with high coupling ratio and low leakage simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the coupling ratio and programming window in planar non-volatile memory devices, preventing program saturation and enabling further voltage scaling while maintaining low leakage, thus improving device performance beyond the 10nm technology node.
Implementation Method 1
the first interfacial layer is formed on the second upper metal layer and comprises a high k-value material having a thickness configured to provide a potential energy drop across the first interfacial layer which is below 0.5eV
Implementation Method 2
the first and third layers having a higher k-value than the second layer which is sandwiched therebetween
Implementation Method 3
An intermediate dielectric layer of a predetermined thickness is used to separate at least two of the layers of floating gate to enable a direct tunnelling current between the two separated layers
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
Described herein is a planar non-volatile memory device (100) having a specifically designed structure comprising a hybrid floating gate structure (120, 125, 130) separated from an inter-gate dielectric structure (150) by a first interfacial layer (140) which is designed to be electrically transparent so as not to affect the program saturation of the device. The inter-gate structure (150) comprises a stack of three layers (155, 160, 165) having a high-k/low-k/high-k configuration and the interfacial layer (140) has a higher k-value than its adjacent high-k layer (155) in the inter-gate dielectric structure (150). A method of making such a non-volatile memory device is also described.