Hybrid Forward Error Correction and Replay for Low Latency
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Solution Overview
Problem
High-speed data transmission in high-performance computing systems faces challenges with increased bit error ratios due to interconnect imperfections and signal loss, where conventional error correction techniques like error correcting codes and packet replay increase latency, necessitating a method to correct errors at higher bit error ratios while maintaining low latency.
Innovation Solution
The implementation of a combination of link-level forward error correction and replay, where forward error correction is used to correct errors below a threshold level, and replay is employed for remaining errors, with a multiplexer determining the correction technique based on error counts and threshold levels to minimize latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correcting codes or packet replay are used to improve error ratio, then reliability is improved, but latency increases
Solution Approach 1:
The system dynamically selects between forward error correction and packet replay techniques based on real-time error conditions. When bit error ratios are within acceptable thresholds, forward error correction is applied; when errors exceed thresholds, packet replay is triggered. This dynamic adaptation resolves the contradiction by optimizing the balance between reliability improvement and latency minimization based on actual channel conditions.
Solution Approach 2:
The invention changes the parameter of error correction strategy based on bit error ratio thresholds. By monitoring error rates and adjusting the correction method (from forward error correction to packet replay) according to error severity, the system achieves reliable error correction while minimizing latency overhead. This parameter-based adaptation allows the system to maintain low latency for minor errors while ensuring reliability for severe error conditions.
2Reliability
If forward error correction is used to correct errors, then reliability is improved, but latency increases quadratically with the number of errors
Solution Approach 1:
The system applies forward error correction only partially - specifically, only when the number of errors in a packet is below a predetermined threshold. For packets with error counts exceeding the threshold, the system switches to packet replay instead. This partial application of forward error correction avoids the quadratic latency penalty while maintaining reliability for correctable error scenarios.
Solution Approach 2:
The error correction process is segmented into two distinct paths: forward error correction for low-error packets and packet replay for high-error packets. This segmentation allows the system to apply the most efficient correction method for each error condition, preventing the quadratic latency increase from affecting all packets regardless of error severity.
3Reliability
If packet replay is used to correct errors, then reliability is improved, but latency increases when bit error ratio is too high or link delay is too high
Solution Approach 1:
The system dynamically determines when to apply packet replay based on monitored bit error ratios and link conditions. By continuously assessing channel quality and error rates, the system triggers packet replay only when necessary (when errors exceed correction capabilities or link delay is excessive), rather than applying it universally. This dynamic approach maintains reliability while minimizing the latency penalty associated with replay operations.
Data Source
AI summary
Disclosed herein are high performance systems with low latency error correction as well as related devices and methods. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction and link level replay, where errors at or below a threshold level are corrected by forward error correction and remaining errors are corrected using replay. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction, link level replay, and a multiplexer for determining which error correction technique to use based on the number of errors and an error threshold level.