Hybrid FPGA-ASIC Code Acceleration Architecture
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Solution Overview
Problem
Current computing devices face challenges in achieving both flexibility and performance efficiency for specialized tasks, as general-purpose processors and hardware accelerators like FPGAs and ASICs often require trade-offs between flexibility and power consumption.
Innovation Solution
A hybrid computing device architecture that combines a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC), where the FPGA offloads service requests and performs algorithmic tasks, while the ASIC handles computationally intensive primitive operations, allowing for flexible algorithm updates and efficient performance similar to an all-ASIC implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a pure ASIC solution is used, then performance and power efficiency are improved, but flexibility and adaptability deteriorate
Solution Approach 1:
The system is segmented into two distinct components: an FPGA portion and an ASIC portion. The FPGA handles algorithmic tasks that require flexibility, while the ASIC handles primitive operations that require high performance and power efficiency. This segmentation allows each component to operate in its optimal regime, resolving the contradiction between flexibility and performance efficiency.
Solution Approach 2:
The hybrid computing device is designed to perform multiple functions by combining the reconfigurable nature of the FPGA with the dedicated functionality of the ASIC. The FPGA can be reconfigured to handle different algorithmic tasks, while the ASIC provides consistent high-performance execution of primitive operations, making the overall system both flexible and efficient across multiple applications.
2Adaptability or versatility
If a pure FPGA solution is used, then flexibility and adaptability are improved, but power consumption increases
Solution Approach 1:
The computing device is divided into an FPGA portion for flexible algorithmic processing and an ASIC portion for power-efficient primitive operation execution. By segmenting the workload according to the strengths of each technology, the system achieves flexibility where needed while reducing overall power consumption through the ASIC's efficient execution of repetitive tasks.
Solution Approach 2:
The power-intensive primitive operations are extracted from the FPGA and offloaded to the ASIC. This extraction removes the energy consumption burden from the FPGA, allowing it to maintain flexibility while the ASIC handles the computationally intensive but power-efficient processing of primitive operations.
3Adaptability or versatility
If algorithmic tasks are performed on the FPGA, then adaptability for updates is improved, but performance efficiency deteriorates
Solution Approach 1:
The computational workload is segmented into algorithmic tasks executed by the FPGA and primitive operations executed by the ASIC. This segmentation allows the FPGA to focus on flexible, updatable algorithmic logic while the ASIC provides high-performance execution of primitive operations, thereby maintaining both adaptability and performance efficiency simultaneously.
Data Source
AI summary
Technologies for hybrid field-programmable gate array (FPGA) application-specific integrated circuit (ASIC) code acceleration are described. In one example, the computing device includes a FPGA comprising: algorithm circuitry to: perform one or more algorithm tasks of an algorithm, wherein the algorithm to perform a service request that is offloaded to the FPGA; and determine a primitive task associated with an algorithm task of the one or more algorithm tasks; primitive offload circuitry to encapsulate the primitive task in a buffer of the FPGA, wherein the buffer is accessible by an ASIC of the computing device; and result circuitry to return one or more results of the service request responsive to performance of the primitive task by the ASIC.