Hybrid Nanosheet-Nanowire GAA Transistors for Higher Functional Density
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Solution Overview
Problem
The scaling down of Integrated Circuits (ICs) has increased complexity in processing and manufacturing, necessitating advancements in Gate-All-Around (GAA) Transistor fabrication.
Innovation Solution
A hybrid structure comprising a nanosheet transistor and a nanowire transistor is formed, where the nanowire transistor thickness is increased through epitaxial growth of semiconductor material, sharing common formation processes to reduce chip area without compromising circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar transistors are used in IC scaling, then manufacturing process complexity increases, but circuit performance and functional density improve
Solution Approach 1:
The patent divides the transistor structure into multiple nanosheets stacked vertically, creating multiple channel regions within a single device footprint. This segmentation approach increases functional density by stacking channels while maintaining a compact structure that simplifies manufacturing compared to traditional planar scaling
Solution Approach 2:
The patent transitions from two-dimensional planar transistor structures to three-dimensional vertically-stacked nanosheet structures. By adding the vertical dimension with multiple stacked channels, the design achieves higher functional density without proportionally increasing manufacturing complexity, as the same fabrication processes can be applied to create the stacked architecture
2Reliability
If GAA transistor structures are implemented, then circuit performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent employs a universal fabrication process that can create both nanosheet and nanowire transistor structures using the same sequence of steps. The nanosheet transistor uses sacrificial layers that are removed to form channels, while the nanowire transistor uses the same process but retains the sacrificial layer structure to form 3D channels, allowing one process to serve multiple device architectures
Solution Approach 2:
The patent applies different structural configurations to different device regions within the same integrated circuit. Some regions contain nanosheet transistors while others contain nanowire transistors, allowing optimization of circuit performance for different functional blocks while using a common fabrication process, thereby managing overall manufacturing complexity
3Productivity
If chip area is reduced for scaling, then production efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent nests multiple nanosheet channels vertically within a compact footprint, with each nanosheet contained within the same lateral boundary. This nesting approach reduces the horizontal chip area required while maintaining manufacturability, as the vertical stacking can be achieved through standard thin-film deposition and etching processes without requiring extreme precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hybrid structure reduces occupied chip area while maintaining circuit performance, addressing the complexity challenges in IC manufacturing.
Implementation Method 1
the thickness of the nanowire transistor channel region is increased by epitaxially growing a semiconductor material
Data Source
AI summary
A method includes patterning stacked layers to form a first multi-layer stack and a second multi-layer stack, each including a plurality of sacrificial layers and a plurality of nanostructures located alternatingly. The second multi-layer stack is wider than the first multi-layer stack. A nanosheet transistor is formed based on the first multi-layer stack. The nanosheet transistor includes first channel regions having a first width, and a first gate stack on the first channel regions. A nanowire transistor is formed based on the second multi-layer stack. The nanowire transistor includes second channel regions narrower than the first channel regions, and a second gate stack on the second channel regions.