Hybrid-Orientation GAA Transistors for Mobility Without Substrate Defects
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Solution Overview
Problem
Current gate-all-around (GAA) CMOS devices face limitations in optimizing both p-type and n-type transistors due to the unsuitability of silicon channels with specific crystallographic orientations, leading to suboptimal performance and defect generation when trying to combine different orientations in the same device.
Innovation Solution
The approach involves bonding silicon wafers with different crystallographic orientations and selectively removing and replacing layers to create a hybrid orientation configuration where p-type transistors have (110) oriented silicon channels and n-type transistors have (100) oriented silicon channels on the same wafer, ensuring they are not vertically stacked but share the same horizontal level, thereby optimizing both hole and electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hybrid orientation of p-type and n-type transistors is formed using existing methods, then device performance is improved, but defects are generated due to substrate issues propagating into the channel
Solution Approach 1:
The patent divides the substrate into multiple independent wafers with different crystallographic orientations. Each wafer is processed separately to form transistors with optimized orientations (e.g., (100) for nFETs, (110) for pFETs), then bonded together. This segmentation prevents substrate defects from propagating across the entire device while maintaining hybrid orientation benefits.
Solution Approach 2:
The patent introduces an intermediary bonding process between wafers with different orientations. A bonding interface is created that allows joining of separately processed wafers, each optimized for specific transistor types. This intermediary structure enables hybrid orientation formation without direct substrate defects affecting the channel regions.
2Reliability
If wafer bonding is performed to create hybrid orientation, then hole and electron mobility are improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary processing of each wafer separately before bonding, including forming alternating layers of silicon and silicon germanium, creating sacrificial layers, and preparing channel structures. This preliminary action on individual wafers simplifies the overall process by avoiding the need to handle complex hybrid structures during fabrication, reducing manufacturing complexity while achieving improved carrier mobility.
Solution Approach 2:
The patent changes the crystallographic orientation parameter of different wafer regions to optimize carrier mobility. By using (100) orientation for nFETs and (110) orientation for pFETs, the patent achieves doubled hole mobility in pFETs and maintains fast electron transport in nFETs. This parameter change is implemented through selective wafer bonding rather than complex in-situ orientation control.
3Reliability
If alternating silicon and silicon germanium layers are formed, then transistor performance is optimized, but manufacturing steps increase
Solution Approach 1:
The patent segments the formation of alternating silicon and silicon germanium layers into separate processes on different wafers. Each wafer receives its own stack of alternating layers with appropriate orientations, which are then bonded together. This segmentation allows parallel processing and simplifies each individual layer formation step, improving manufacturing efficiency while maintaining optimized transistor performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly improves device performance by doubling hole mobility for pFETs and enhancing transport capabilities, overcoming previous limitations of defect generation and unsatisfactory results from previous methods, resulting in a hybrid orientation that optimizes both p-type and n-type transistor performance.
Implementation Method 1
bonding a first wafer including a first silicon substrate having a first crystallographic orientation to a second wafer including a second silicon substrate having a second crystallographic orientation
Data Source
AI summary
A semiconductor device includes a p-type field-effect transistor including first channels made of silicon having a (110) crystallographic orientation. The semiconductor device further includes an n-type field-effect transistor including second channels made of silicon having a (100) crystallographic orientation. The semiconductor device further includes a gate surrounding the first channels and the second channels.