Hybrid GAA Nanostructure Layout for High-Speed and Low-Power Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing techniques have not satisfactorily addressed the challenge of providing multi-gate devices, such as GAA transistors, that meet diverse device performance requirements while maintaining satisfactory strain performance and low leakage current.
Innovation Solution
A hybrid nanostructure scheme is implemented to form semiconductor structures with both high-speed and low-power GAA transistors by configuring different numbers of effective channel layers coupled to corresponding source/drain features, along with a vertical sidewall dielectric layer for isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate devices are introduced to improve gate control and reduce off-state current, then device performance is improved, but device complexity increases
Solution Approach 1:
The channel region is segmented into multiple discrete nanostructures (nanowires, nanosheets, or quantum wells) stacked vertically, with each nanostructure forming a separate gate-controlled channel. This segmentation enables improved gate control through multi-sided wrapping while maintaining manageable device complexity through modular stacking architecture
Solution Approach 2:
The device transitions from planar 2D channel geometry to vertical 3D stacked nanostructures, allowing the gate to wrap around channels on multiple sides (top and sidewalls). This dimensional change enhances gate control efficiency while organizing complexity vertically rather than horizontally
2Adaptability or versatility
If different device types with different performance requirements are integrated, then versatility is improved, but manufacturing precision requirements increase
Solution Approach 1:
Different regions of the semiconductor structure are engineered with distinct properties: some nanostructures are configured for high-speed performance while others optimize for low-power operation. The gate structure, channel materials, and doping profiles are locally tailored to meet specific performance requirements of each device type within the same integrated system
Solution Approach 2:
The integrated circuit is divided into separate device regions, each containing nanostructures optimized for specific performance characteristics. This segmentation allows independent optimization of high-speed and low-power devices while using standardized fabrication processes, thereby managing manufacturing precision requirements
Data Source
AI summary
Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a first transistor. The first transistor includes a first gate structure wrapping around a plurality of first nanostructures disposed over a substrate, a first source/drain feature electrically coupled to a topmost nanostructure of the plurality of first nanostructures and isolated from a bottommost nanostructure of the plurality of first nanostructures by a first dielectric layer, and a first semiconductor layer disposed between the substrate and the first source/drain feature, wherein the first source/drain feature is in direct contact with a top surface of the first semiconductor layer.