Hybrid Metal Gate Capping Layer for Lower Gate Resistance
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Solution Overview
Problem
Metal-Oxide-Semiconductor (MOS) devices with polysilicon gate electrodes suffer from the carrier depletion effect, known as poly depletion, which increases the effective gate dielectric thickness and makes it difficult to create an inversion layer, limiting the performance of transistors.
Innovation Solution
The formation of metal gate electrodes with a hybrid capping layer comprising a first low-resistivity conductive layer as a seed layer, followed by a second low-resistivity conductive layer, which reduces the overall gate resistance and mitigates the poly depletion effect by selectively depositing these layers on the metal gate, thereby improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon gate electrodes are used to adjust work function, then the work function can be adjusted to band-edge, but carrier depletion effect occurs increasing effective gate dielectric thickness
Solution Approach 1:
The patent changes the material parameter from polysilicon to metal (TiN, TaN, WN) to fundamentally alter the electrical properties. Metal gates eliminate the carrier depletion effect by providing high carrier density, thereby changing the gate electrode's electrical conductivity parameter from semiconducting to metallic while maintaining work function adjustability through material selection and thickness control.
Solution Approach 2:
The patent employs composite gate electrode structures combining multiple metal layers (e.g., TiN/TaN, TiN/Al, WN/TiN) to achieve both work function adjustment and elimination of depletion effects. The composite structure allows each layer to contribute specific properties: TiN provides adhesion and barrier functions, TaN/WN provide work function control, and the metal combination eliminates poly depletion while maintaining electrical performance.
2Object-affected harmful factors
If metal gate electrodes are formed to solve poly depletion, then carrier depletion effect is eliminated, but gate resistance increases
Solution Approach 1:
The patent uses composite metal gate structures where highly conductive metal layers (TiN, TaN, WN) are combined in specific configurations. These composite structures provide both the depletion-free operation of metal gates and low resistance through the inherent conductivity of the metal materials, replacing the high-resistance polysilicon while eliminating depletion effects.
Solution Approach 2:
The patent changes the electrical conductivity parameter by transitioning from polysilicon to metal materials. The metal gate electrodes exhibit significantly higher carrier density and electrical conductivity, thereby reducing gate resistance while eliminating the carrier depletion effect that plagues polysilicon gates.
3Adaptability or versatility
If multiple metal layers are used to achieve band-edge work functions, then NMOS and PMOS requirements are met, but device complexity increases
Solution Approach 1:
The patent achieves work function adjustment by changing material composition parameters rather than structural complexity. Different metal materials (TiN, TaN, WN) with specific thicknesses provide different work functions, allowing n-type and p-type device requirements to be met through material selection rather than complex multi-layer configurations. This simplifies the overall device structure while maintaining the required electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of hybrid capping layers in metal gate electrodes reduces gate resistance and enhances the ability to form inversion layers, improving the performance and efficiency of MOS devices by addressing the poly depletion issue.
Implementation Method 1
selectively depositing these layers on the metal gate
Data Source
AI summary
A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.