Hybrid Self-Aligned Gate Cut for Precise Transistor Isolation
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Solution Overview
Problem
As integrated circuits scale downward in size, forming semiconductor devices with precise gate cuts to isolate adjacent transistors becomes challenging due to the difficulty in maintaining selectivity during deep etches, especially for high-aspect ratio structures.
Innovation Solution
A hybrid self-aligned gate cut technique is employed, where a first section of the gate cut is self-aligned between adjacent fins before gate patterning, and a second section is formed on the first section after the formation of a sacrificial gate, using a seamless integration with spacer structures to ensure precise isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep etches are used to form gate cuts for isolating adjacent transistors, then isolation between devices is achieved, but manufacturing precision deteriorates due to difficulty in maintaining selectivity during deep etches
Solution Approach 1:
The gate cut formation process is divided into two separate etching stages: a first etch that creates an initial gate cut through the gate dielectric and gate electrode, and a second etch that completes the gate cut through the remaining structures. This segmentation allows each etch to be optimized independently, maintaining precision while achieving complete isolation.
Solution Approach 2:
The first gate cut is formed as a preliminary action before the second etch. This preliminary gate cut serves as a guide and reference for the subsequent second etch, ensuring that the final gate cut maintains precise alignment and dimensions. The preliminary structure also helps establish the correct depth and position for the completing etch.
2Productivity
If device spacing is reduced to increase transistor density, then productivity improves, but manufacturing precision deteriorates due to challenges in forming isolation structures at reduced spacing
Solution Approach 1:
The solution moves from attempting to form complete gate cuts in a single vertical etch to a two-stage process that first establishes the cut in upper layers, then completes it in lower layers. This dimensional approach to etching allows precise control at reduced device spacings by addressing different depth zones separately with optimized etch parameters for each stage.
Data Source
AI summary
Techniques are provided herein to form semiconductor devices that include one or more self-aligned gate cuts having a hybrid architecture between adjacent devices. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region (also referred to as a channel region). The gate structure may be interrupted between two transistors with a gate cut that extends through at least an entire thickness of the gate structure and includes dielectric material. The gate cut includes a hybrid design that is formed in two parts. A first part of the gate cut is formed prior to any gate patterning and is self-aligned between adjacent fins of semiconductor material. A second part of the gate cut is formed over the first part of the gate cut and is integrated with spacer structures formed on the sidewalls of a sacrificial gate that extends over the adjacent fins.