Hybrid Gate Isolation Structures for Memory and Logic Arrays
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Solution Overview
Problem
Existing IC manufacturing methods fail to provide satisfactory gate isolation structures that meet the different performance requirements of memory and logic arrays, leading to issues such as parasitic capacitance and threshold voltage variation.
Innovation Solution
The formation of hybrid gate isolation structures, where memory arrays use nitrogen-containing dielectric materials with low oxygen concentration and logic arrays use low-k dielectric materials, to achieve reduced parasitic capacitance and threshold voltage variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single type of gate isolation structure is used for both memory and logic arrays, then manufacturing process is simplified, but performance requirements of different arrays cannot be met
Solution Approach 1:
The patent applies local quality by implementing different gate isolation structures in different regions of the IC chip. Memory arrays use first gate isolation structures with specific dielectric materials optimized for low threshold voltage variation, while logic arrays use second gate isolation structures with different dielectric materials optimized for low parasitic capacitance. This allows each region to have the properties needed for its specific function.
Solution Approach 2:
The patent segments the gate isolation structures into at least two distinct types: first gate isolation structures for memory arrays and second gate isolation structures for logic arrays. This segmentation enables independent optimization of each structure type for its specific application requirements while maintaining overall system functionality.
2Reliability
If nitrogen-containing dielectric materials with low oxygen concentration are used in memory arrays, then threshold voltage variation is minimized, but parasitic capacitance in logic arrays increases
Solution Approach 1:
The patent applies local quality by implementing different gate isolation structures in different regions of the IC chip. Memory arrays use first gate isolation structures with specific dielectric materials optimized for low threshold voltage variation, while logic arrays use second gate isolation structures with different dielectric materials optimized for low parasitic capacitance. This allows each region to have the properties needed for its specific function.
Solution Approach 2:
The patent changes the dielectric material parameters between different gate isolation structures. First gate isolation structures use nitrogen-containing dielectric materials with low oxygen concentration to minimize threshold voltage variation in memory arrays. Second gate isolation structures use low-k dielectric materials to minimize parasitic capacitance in logic arrays. This parameter change enables optimization for different performance requirements.
3Object-generated harmful factors
If low-k dielectric materials are used in logic arrays, then parasitic capacitance is reduced, but threshold voltage variation in memory arrays increases
Solution Approach 1:
The patent applies local quality by implementing different gate isolation structures in different regions of the IC chip. Memory arrays use first gate isolation structures with specific dielectric materials optimized for low threshold voltage variation, while logic arrays use second gate isolation structures with different dielectric materials optimized for low parasitic capacitance. This allows each region to have the properties needed for its specific function.
Solution Approach 2:
The patent changes the dielectric material parameters between different gate isolation structures. First gate isolation structures use nitrogen-containing dielectric materials with low oxygen concentration to minimize threshold voltage variation in memory arrays. Second gate isolation structures use low-k dielectric materials to minimize parasitic capacitance in logic arrays. This parameter change enables optimization for different performance requirements.
4Adaptability or versatility
If hybrid gate isolation structures are implemented, then performance requirements of both arrays are met, but manufacturing complexity increases
Solution Approach 1:
The patent segments the gate isolation structures into at least two distinct types: first gate isolation structures for memory arrays and second gate isolation structures for logic arrays. This segmentation enables independent optimization of each structure type for its specific application requirements while maintaining overall system functionality.
Solution Approach 2:
The patent forms the first and second gate isolation structures before forming the metal gate structures. This preliminary action allows the isolation structures to be in place and properly configured before subsequent processing steps, simplifying the overall manufacturing process by establishing isolation requirements early in the fabrication sequence.
Data Source
AI summary
An IC structure and a method of forming the same are provided. In an embodiment, an exemplary method of forming the IC structure forming a high-k metal gate structure extending lengthwise along a first direction, forming a trench to separate the high-k metal gate structure into two portions, conformally depositing a first dielectric layer to substantially fill the trench, after the conformally depositing of the first dielectric layer, forming a patterned mask over the high-k metal gate structure, the patterned mask comprising an opening disposed directly over the trench, etching back the first dielectric layer while using the patterned mask as an etch mask to obtain a thinned first dielectric layer, and after the etching of the first dielectric layer, forming a second dielectric layer in the trench and on the thinned first dielectric layer.